Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> |
Michal Simek | 98d0f1f | 2018-01-17 07:37:47 +0100 | [diff] [blame] | 4 | * (C) Copyright 2013 - 2018 Xilinx, Inc. |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 8 | #include <dm/uclass.h> |
Michal Simek | 65ef52f | 2014-02-24 11:16:32 +0100 | [diff] [blame] | 9 | #include <fdtdec.h> |
Michal Simek | 0f79670 | 2014-04-25 13:51:17 +0200 | [diff] [blame] | 10 | #include <fpga.h> |
| 11 | #include <mmc.h> |
Michal Simek | c07b225 | 2018-06-08 13:45:14 +0200 | [diff] [blame] | 12 | #include <watchdog.h> |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 13 | #include <wdt.h> |
Michal Simek | 15d654c | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 14 | #include <zynqpl.h> |
Michal Simek | 242192b | 2013-04-12 16:33:08 +0200 | [diff] [blame] | 15 | #include <asm/arch/hardware.h> |
| 16 | #include <asm/arch/sys_proto.h> |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 20 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) |
| 21 | static struct udevice *watchdog_dev; |
| 22 | #endif |
| 23 | |
| 24 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) |
| 25 | int board_early_init_f(void) |
| 26 | { |
| 27 | # if defined(CONFIG_WDT) |
| 28 | /* bss is not cleared at time when watchdog_reset() is called */ |
| 29 | watchdog_dev = NULL; |
| 30 | # endif |
| 31 | |
| 32 | return 0; |
| 33 | } |
| 34 | #endif |
| 35 | |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 36 | int board_init(void) |
| 37 | { |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 38 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) |
Michal Simek | 41e905b | 2018-07-11 08:35:22 +0200 | [diff] [blame] | 39 | if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { |
| 40 | debug("Watchdog: Not found by seq!\n"); |
| 41 | if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { |
| 42 | puts("Watchdog: Not found!\n"); |
| 43 | return 0; |
| 44 | } |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 45 | } |
Michal Simek | 41e905b | 2018-07-11 08:35:22 +0200 | [diff] [blame] | 46 | |
| 47 | wdt_start(watchdog_dev, 0, 0); |
| 48 | puts("Watchdog: Started\n"); |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 49 | # endif |
| 50 | |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 51 | return 0; |
| 52 | } |
| 53 | |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 54 | int board_late_init(void) |
| 55 | { |
| 56 | switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { |
Michal Simek | 1935671 | 2016-12-16 13:16:14 +0100 | [diff] [blame] | 57 | case ZYNQ_BM_QSPI: |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 58 | env_set("modeboot", "qspiboot"); |
Michal Simek | 1935671 | 2016-12-16 13:16:14 +0100 | [diff] [blame] | 59 | break; |
| 60 | case ZYNQ_BM_NAND: |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 61 | env_set("modeboot", "nandboot"); |
Michal Simek | 1935671 | 2016-12-16 13:16:14 +0100 | [diff] [blame] | 62 | break; |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 63 | case ZYNQ_BM_NOR: |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 64 | env_set("modeboot", "norboot"); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 65 | break; |
| 66 | case ZYNQ_BM_SD: |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 67 | env_set("modeboot", "sdboot"); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 68 | break; |
| 69 | case ZYNQ_BM_JTAG: |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 70 | env_set("modeboot", "jtagboot"); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 71 | break; |
| 72 | default: |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 73 | env_set("modeboot", ""); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 74 | break; |
| 75 | } |
| 76 | |
| 77 | return 0; |
| 78 | } |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 79 | |
Joe Hershberger | 7f4e555 | 2016-01-26 11:57:03 -0600 | [diff] [blame] | 80 | int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) |
| 81 | { |
| 82 | #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ |
| 83 | defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) |
| 84 | if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, |
| 85 | CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, |
| 86 | ethaddr, 6)) |
| 87 | printf("I2C EEPROM MAC address read failed\n"); |
| 88 | #endif |
| 89 | |
| 90 | return 0; |
| 91 | } |
| 92 | |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 93 | #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 94 | int dram_init_banksize(void) |
Nathan Rossi | c12892b | 2016-12-04 19:33:22 +1000 | [diff] [blame] | 95 | { |
Michal Simek | d5b7de6 | 2017-11-03 15:25:51 +0100 | [diff] [blame] | 96 | return fdtdec_setup_memory_banksize(); |
Tom Rini | edcfdbd | 2016-12-09 07:56:54 -0500 | [diff] [blame] | 97 | } |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 98 | |
Tom Rini | edcfdbd | 2016-12-09 07:56:54 -0500 | [diff] [blame] | 99 | int dram_init(void) |
| 100 | { |
Nathan Rossi | 58ea0d8 | 2016-12-19 00:03:34 +1000 | [diff] [blame] | 101 | if (fdtdec_setup_memory_size() != 0) |
| 102 | return -EINVAL; |
Tom Rini | edcfdbd | 2016-12-09 07:56:54 -0500 | [diff] [blame] | 103 | |
| 104 | zynq_ddrc_init(); |
| 105 | |
| 106 | return 0; |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 107 | } |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 108 | #else |
| 109 | int dram_init(void) |
| 110 | { |
Michal Simek | 1b84621 | 2018-04-11 16:12:28 +0200 | [diff] [blame] | 111 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
| 112 | CONFIG_SYS_SDRAM_SIZE); |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 113 | |
Michal Simek | f5ff7bc | 2013-06-17 14:37:01 +0200 | [diff] [blame] | 114 | zynq_ddrc_init(); |
| 115 | |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 116 | return 0; |
| 117 | } |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 118 | #endif |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 119 | |
| 120 | #if defined(CONFIG_WATCHDOG) |
| 121 | /* Called by macro WATCHDOG_RESET */ |
| 122 | void watchdog_reset(void) |
| 123 | { |
| 124 | # if !defined(CONFIG_SPL_BUILD) |
| 125 | static ulong next_reset; |
| 126 | ulong now; |
| 127 | |
| 128 | if (!watchdog_dev) |
| 129 | return; |
| 130 | |
| 131 | now = timer_get_us(); |
| 132 | |
| 133 | /* Do not reset the watchdog too often */ |
| 134 | if (now > next_reset) { |
| 135 | wdt_reset(watchdog_dev); |
| 136 | next_reset = now + 1000; |
| 137 | } |
| 138 | # endif |
| 139 | } |
| 140 | #endif |