Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef __GDSYS_FPGA_H |
| 25 | #define __GDSYS_FPGA_H |
| 26 | |
Dirk Eibach | 6fabe55 | 2011-10-20 11:12:55 +0200 | [diff] [blame] | 27 | int init_func_fpga(void); |
| 28 | |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 29 | enum { |
| 30 | FPGA_STATE_DONE_FAILED = 1 << 0, |
| 31 | FPGA_STATE_REFLECTION_FAILED = 1 << 1, |
Dirk Eibach | 6fabe55 | 2011-10-20 11:12:55 +0200 | [diff] [blame] | 32 | FPGA_STATE_PLATFORM = 1 << 2, |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 33 | }; |
| 34 | |
| 35 | int get_fpga_state(unsigned dev); |
| 36 | void print_fpga_state(unsigned dev); |
| 37 | |
| 38 | typedef struct ihs_gpio { |
| 39 | u16 read; |
| 40 | u16 clear; |
| 41 | u16 set; |
| 42 | } ihs_gpio_t; |
| 43 | |
| 44 | typedef struct ihs_i2c { |
| 45 | u16 write_mailbox; |
| 46 | u16 write_mailbox_ext; |
| 47 | u16 read_mailbox; |
| 48 | u16 read_mailbox_ext; |
| 49 | } ihs_i2c_t; |
| 50 | |
| 51 | typedef struct ihs_osd { |
| 52 | u16 version; |
| 53 | u16 features; |
| 54 | u16 control; |
| 55 | u16 xy_size; |
Dirk Eibach | d3b1700 | 2011-04-06 13:53:47 +0200 | [diff] [blame] | 56 | u16 xy_scale; |
| 57 | u16 x_pos; |
| 58 | u16 y_pos; |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 59 | } ihs_osd_t; |
| 60 | |
| 61 | #ifdef CONFIG_IO |
| 62 | typedef struct ihs_fpga { |
| 63 | u16 reflection_low; /* 0x0000 */ |
| 64 | u16 versions; /* 0x0002 */ |
| 65 | u16 fpga_features; /* 0x0004 */ |
| 66 | u16 fpga_version; /* 0x0006 */ |
| 67 | u16 reserved_0[5]; /* 0x0008 */ |
| 68 | u16 quad_serdes_reset; /* 0x0012 */ |
| 69 | u16 reserved_1[8181]; /* 0x0014 */ |
| 70 | u16 reflection_high; /* 0x3ffe */ |
| 71 | } ihs_fpga_t; |
| 72 | #endif |
| 73 | |
Dirk Eibach | 6fabe55 | 2011-10-20 11:12:55 +0200 | [diff] [blame] | 74 | #ifdef CONFIG_IO64 |
| 75 | typedef struct ihs_fpga { |
| 76 | u16 reflection_low; /* 0x0000 */ |
| 77 | u16 versions; /* 0x0002 */ |
| 78 | u16 fpga_features; /* 0x0004 */ |
| 79 | u16 fpga_version; /* 0x0006 */ |
| 80 | u16 reserved_0[5]; /* 0x0008 */ |
| 81 | u16 quad_serdes_reset; /* 0x0012 */ |
| 82 | u16 reserved_1[502]; /* 0x0014 */ |
| 83 | u16 ch0_status_int; /* 0x0400 */ |
| 84 | u16 ch0_config_int; /* 0x0402 */ |
Dirk Eibach | 6e2350f | 2012-01-02 11:02:46 +0100 | [diff] [blame] | 85 | u16 reserved_2[126]; /* 0x0404 */ |
| 86 | u16 ch0_hicb_status_int;/* 0x0500 */ |
| 87 | u16 ch0_hicb_config_int;/* 0x0502 */ |
| 88 | u16 reserved_3[7549]; /* 0x0504 */ |
Dirk Eibach | 6fabe55 | 2011-10-20 11:12:55 +0200 | [diff] [blame] | 89 | u16 reflection_high; /* 0x3ffe */ |
| 90 | } ihs_fpga_t; |
| 91 | #endif |
| 92 | |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 93 | #ifdef CONFIG_IOCON |
| 94 | typedef struct ihs_fpga { |
| 95 | u16 reflection_low; /* 0x0000 */ |
| 96 | u16 versions; /* 0x0002 */ |
| 97 | u16 fpga_version; /* 0x0004 */ |
| 98 | u16 fpga_features; /* 0x0006 */ |
| 99 | u16 reserved_0[6]; /* 0x0008 */ |
| 100 | ihs_gpio_t gpio; /* 0x0014 */ |
| 101 | u16 mpc3w_control; /* 0x001a */ |
| 102 | u16 reserved_1[19]; /* 0x001c */ |
| 103 | u16 videocontrol; /* 0x0042 */ |
| 104 | u16 reserved_2[93]; /* 0x0044 */ |
| 105 | u16 reflection_high; /* 0x00fe */ |
| 106 | ihs_osd_t osd; /* 0x0100 */ |
Dirk Eibach | d3b1700 | 2011-04-06 13:53:47 +0200 | [diff] [blame] | 107 | u16 reserved_3[88]; /* 0x010e */ |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 108 | u16 videomem; /* 0x0800 */ |
| 109 | } ihs_fpga_t; |
| 110 | #endif |
| 111 | |
| 112 | #ifdef CONFIG_DLVISION_10G |
| 113 | typedef struct ihs_fpga { |
| 114 | u16 reflection_low; /* 0x0000 */ |
| 115 | u16 versions; /* 0x0002 */ |
| 116 | u16 fpga_version; /* 0x0004 */ |
| 117 | u16 fpga_features; /* 0x0006 */ |
| 118 | u16 reserved_0[10]; /* 0x0008 */ |
| 119 | u16 extended_interrupt; /* 0x001c */ |
| 120 | u16 reserved_1[9]; /* 0x001e */ |
| 121 | ihs_i2c_t i2c; /* 0x0030 */ |
Dirk Eibach | c0413ee | 2011-04-06 13:53:48 +0200 | [diff] [blame] | 122 | u16 reserved_2[16]; /* 0x0038 */ |
| 123 | u16 mpc3w_control; /* 0x0058 */ |
| 124 | u16 reserved_3[34]; /* 0x005a */ |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 125 | u16 videocontrol; /* 0x009e */ |
Dirk Eibach | c0413ee | 2011-04-06 13:53:48 +0200 | [diff] [blame] | 126 | u16 reserved_4[176]; /* 0x00a0 */ |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 127 | ihs_osd_t osd; /* 0x0200 */ |
Dirk Eibach | c0413ee | 2011-04-06 13:53:48 +0200 | [diff] [blame] | 128 | u16 reserved_5[761]; /* 0x020e */ |
Dirk Eibach | 81b3793 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 129 | u16 videomem; /* 0x0800 */ |
| 130 | } ihs_fpga_t; |
| 131 | #endif |
| 132 | |
| 133 | #endif |