| HeungJun, Kim | b371727 | 2012-01-16 21:13:04 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Samsung Electronics |
| 3 | * Heungjun Kim <riverful.kim@samsung.com> |
| 4 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| HeungJun, Kim | b371727 | 2012-01-16 21:13:04 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __ASM_ARM_ARCH_POWER_H_ |
| 9 | #define __ASM_ARM_ARCH_POWER_H_ |
| 10 | |
| 11 | #ifndef __ASSEMBLY__ |
| 12 | struct exynos4_power { |
| 13 | unsigned int om_stat; |
| 14 | unsigned char res1[0x8]; |
| 15 | unsigned int rtc_clko_sel; |
| 16 | unsigned int gnss_rtc_out_ctrl; |
| 17 | unsigned char res2[0x1ec]; |
| 18 | unsigned int system_power_down_ctrl; |
| 19 | unsigned char res3[0x1]; |
| 20 | unsigned int system_power_down_option; |
| 21 | unsigned char res4[0x1f4]; |
| 22 | unsigned int swreset; |
| 23 | unsigned int rst_stat; |
| 24 | unsigned char res5[0x1f8]; |
| 25 | unsigned int wakeup_stat; |
| 26 | unsigned int eint_wakeup_mask; |
| 27 | unsigned int wakeup_mask; |
| 28 | unsigned char res6[0xf4]; |
| 29 | unsigned int hdmi_phy_control; |
| 30 | unsigned int usbdevice_phy_control; |
| 31 | unsigned int usbhost_phy_control; |
| 32 | unsigned int dac_phy_control; |
| 33 | unsigned int mipi_phy0_control; |
| 34 | unsigned int mipi_phy1_control; |
| 35 | unsigned int adc_phy_control; |
| 36 | unsigned int pcie_phy_control; |
| 37 | unsigned int sata_phy_control; |
| 38 | unsigned char res7[0xdc]; |
| 39 | unsigned int inform0; |
| 40 | unsigned int inform1; |
| 41 | unsigned int inform2; |
| 42 | unsigned int inform3; |
| 43 | unsigned int inform4; |
| 44 | unsigned int inform5; |
| 45 | unsigned int inform6; |
| 46 | unsigned int inform7; |
| 47 | unsigned char res8[0x1e0]; |
| 48 | unsigned int pmu_debug; |
| 49 | unsigned char res9[0x5fc]; |
| 50 | unsigned int arm_core0_sys_pwr_reg; |
| 51 | unsigned char res10[0xc]; |
| 52 | unsigned int arm_core1_sys_pwr_reg; |
| 53 | unsigned char res11[0x6c]; |
| 54 | unsigned int arm_common_sys_pwr_reg; |
| 55 | unsigned char res12[0x3c]; |
| 56 | unsigned int arm_cpu_l2_0_sys_pwr_reg; |
| 57 | unsigned int arm_cpu_l2_1_sys_pwr_reg; |
| 58 | unsigned char res13[0x38]; |
| 59 | unsigned int cmu_aclkstop_sys_pwr_reg; |
| 60 | unsigned int cmu_sclkstop_sys_pwr_reg; |
| 61 | unsigned char res14[0x4]; |
| 62 | unsigned int cmu_reset_sys_pwr_reg; |
| 63 | unsigned char res15[0x10]; |
| 64 | unsigned int apll_sysclk_sys_pwr_reg; |
| 65 | unsigned int mpll_sysclk_sys_pwr_reg; |
| 66 | unsigned int vpll_sysclk_sys_pwr_reg; |
| 67 | unsigned int epll_sysclk_sys_pwr_reg; |
| 68 | unsigned char res16[0x8]; |
| 69 | unsigned int cmu_clkstop_gps_alive_sys_pwr_reg; |
| 70 | unsigned int cmu_reset_gps_alive_sys_pwr_reg; |
| 71 | unsigned int cmu_clkstop_cam_sys_pwr_reg; |
| 72 | unsigned int cmu_clkstop_tv_sys_pwr_reg; |
| 73 | unsigned int cmu_clkstop_mfc_sys_pwr_reg; |
| 74 | unsigned int cmu_clkstop_g3d_sys_pwr_reg; |
| 75 | unsigned int cmu_clkstop_lcd0_sys_pwr_reg; |
| 76 | unsigned int cmu_clkstop_lcd1_sys_pwr_reg; |
| 77 | unsigned int cmu_clkstop_maudio_sys_pwr_reg; |
| 78 | unsigned int cmu_clkstop_gps_sys_pwr_reg; |
| 79 | unsigned int cmu_reset_cam_sys_pwr_reg; |
| 80 | unsigned int cmu_reset_tv_sys_pwr_reg; |
| 81 | unsigned int cmu_reset_mfc_sys_pwr_reg; |
| 82 | unsigned int cmu_reset_g3d_sys_pwr_reg; |
| 83 | unsigned int cmu_reset_lcd0_sys_pwr_reg; |
| 84 | unsigned int cmu_reset_lcd1_sys_pwr_reg; |
| 85 | unsigned int cmu_reset_maudio_sys_pwr_reg; |
| 86 | unsigned int cmu_reset_gps_sys_pwr_reg; |
| 87 | unsigned int top_bus_sys_pwr_reg; |
| 88 | unsigned int top_retention_sys_pwr_reg; |
| 89 | unsigned int top_pwr_sys_pwr_reg; |
| 90 | unsigned char res17[0x1c]; |
| 91 | unsigned int logic_reset_sys_pwr_reg; |
| 92 | unsigned char res18[0x14]; |
| 93 | unsigned int onenandxl_mem_sys_pwr_reg; |
| 94 | unsigned int modemif_mem_sys_pwr_reg; |
| 95 | unsigned char res19[0x4]; |
| 96 | unsigned int usbdevice_mem_sys_pwr_reg; |
| 97 | unsigned int sdmmc_mem_sys_pwr_reg; |
| 98 | unsigned int cssys_mem_sys_pwr_reg; |
| 99 | unsigned int secss_mem_sys_pwr_reg; |
| 100 | unsigned char res20[0x4]; |
| 101 | unsigned int pcie_mem_sys_pwr_reg; |
| 102 | unsigned int sata_mem_sys_pwr_reg; |
| 103 | unsigned char res21[0x18]; |
| 104 | unsigned int pad_retention_dram_sys_pwr_reg; |
| 105 | unsigned int pad_retention_maudio_sys_pwr_reg; |
| 106 | unsigned char res22[0x18]; |
| 107 | unsigned int pad_retention_gpio_sys_pwr_reg; |
| 108 | unsigned int pad_retention_uart_sys_pwr_reg; |
| 109 | unsigned int pad_retention_mmca_sys_pwr_reg; |
| 110 | unsigned int pad_retention_mmcb_sys_pwr_reg; |
| 111 | unsigned int pad_retention_ebia_sys_pwr_reg; |
| 112 | unsigned int pad_retention_ebib_sys_pwr_reg; |
| 113 | unsigned char res23[0x8]; |
| 114 | unsigned int pad_isolation_sys_pwr_reg; |
| 115 | unsigned char res24[0x1c]; |
| 116 | unsigned int pad_alv_sel_sys_pwr_reg; |
| 117 | unsigned char res25[0x1c]; |
| 118 | unsigned int xusbxti_sys_pwr_reg; |
| 119 | unsigned int xxti_sys_pwr_reg; |
| 120 | unsigned char res26[0x38]; |
| 121 | unsigned int ext_regulator_sys_pwr_reg; |
| 122 | unsigned char res27[0x3c]; |
| 123 | unsigned int gpio_mode_sys_pwr_reg; |
| 124 | unsigned char res28[0x3c]; |
| 125 | unsigned int gpio_mode_maudio_sys_pwr_reg; |
| 126 | unsigned char res29[0x3c]; |
| 127 | unsigned int cam_sys_pwr_reg; |
| 128 | unsigned int tv_sys_pwr_reg; |
| 129 | unsigned int mfc_sys_pwr_reg; |
| 130 | unsigned int g3d_sys_pwr_reg; |
| 131 | unsigned int lcd0_sys_pwr_reg; |
| 132 | unsigned int lcd1_sys_pwr_reg; |
| 133 | unsigned int maudio_sys_pwr_reg; |
| 134 | unsigned int gps_sys_pwr_reg; |
| 135 | unsigned int gps_alive_sys_pwr_reg; |
| 136 | unsigned char res30[0xc5c]; |
| 137 | unsigned int arm_core0_configuration; |
| 138 | unsigned int arm_core0_status; |
| 139 | unsigned int arm_core0_option; |
| 140 | unsigned char res31[0x74]; |
| 141 | unsigned int arm_core1_configuration; |
| 142 | unsigned int arm_core1_status; |
| 143 | unsigned int arm_core1_option; |
| 144 | unsigned char res32[0x37c]; |
| 145 | unsigned int arm_common_option; |
| 146 | unsigned char res33[0x1f4]; |
| 147 | unsigned int arm_cpu_l2_0_configuration; |
| 148 | unsigned int arm_cpu_l2_0_status; |
| 149 | unsigned char res34[0x18]; |
| 150 | unsigned int arm_cpu_l2_1_configuration; |
| 151 | unsigned int arm_cpu_l2_1_status; |
| 152 | unsigned char res35[0xa00]; |
| 153 | unsigned int pad_retention_maudio_option; |
| 154 | unsigned char res36[0xdc]; |
| 155 | unsigned int pad_retention_gpio_option; |
| 156 | unsigned char res37[0x1c]; |
| 157 | unsigned int pad_retention_uart_option; |
| 158 | unsigned char res38[0x1c]; |
| 159 | unsigned int pad_retention_mmca_option; |
| 160 | unsigned char res39[0x1c]; |
| 161 | unsigned int pad_retention_mmcb_option; |
| 162 | unsigned char res40[0x1c]; |
| 163 | unsigned int pad_retention_ebia_option; |
| 164 | unsigned char res41[0x1c]; |
| 165 | unsigned int pad_retention_ebib_option; |
| 166 | unsigned char res42[0x160]; |
| 167 | unsigned int ps_hold_control; |
| 168 | unsigned char res43[0xf0]; |
| 169 | unsigned int xusbxti_configuration; |
| 170 | unsigned int xusbxti_status; |
| 171 | unsigned char res44[0x14]; |
| 172 | unsigned int xusbxti_duration; |
| 173 | unsigned int xxti_configuration; |
| 174 | unsigned int xxti_status; |
| 175 | unsigned char res45[0x14]; |
| 176 | unsigned int xxti_duration; |
| 177 | unsigned char res46[0x1dc]; |
| 178 | unsigned int ext_regulator_duration; |
| 179 | unsigned char res47[0x5e0]; |
| 180 | unsigned int cam_configuration; |
| 181 | unsigned int cam_status; |
| 182 | unsigned int cam_option; |
| 183 | unsigned char res48[0x14]; |
| 184 | unsigned int tv_configuration; |
| 185 | unsigned int tv_status; |
| 186 | unsigned int tv_option; |
| 187 | unsigned char res49[0x14]; |
| 188 | unsigned int mfc_configuration; |
| 189 | unsigned int mfc_status; |
| 190 | unsigned int mfc_option; |
| 191 | unsigned char res50[0x14]; |
| 192 | unsigned int g3d_configuration; |
| 193 | unsigned int g3d_status; |
| 194 | unsigned int g3d_option; |
| 195 | unsigned char res51[0x14]; |
| 196 | unsigned int lcd0_configuration; |
| 197 | unsigned int lcd0_status; |
| 198 | unsigned int lcd0_option; |
| 199 | unsigned char res52[0x14]; |
| 200 | unsigned int lcd1_configuration; |
| 201 | unsigned int lcd1_status; |
| 202 | unsigned int lcd1_option; |
| 203 | unsigned char res53[0x34]; |
| 204 | unsigned int gps_configuration; |
| 205 | unsigned int gps_status; |
| 206 | unsigned int gps_option; |
| 207 | unsigned char res54[0x14]; |
| 208 | unsigned int gps_alive_configuration; |
| 209 | unsigned int gps_alive_status; |
| 210 | unsigned int gps_alive_option; |
| 211 | }; |
| Rajeshwari Shinde | 8b39a6e | 2012-05-14 05:52:01 +0000 | [diff] [blame] | 212 | |
| 213 | struct exynos5_power { |
| 214 | unsigned int om_stat; |
| 215 | unsigned char res1[0x18]; |
| 216 | unsigned int rtc_clko_sel; |
| 217 | unsigned int gnss_rtc_out_ctrl; |
| 218 | unsigned char res2[0x1dc]; |
| 219 | unsigned int central_seq_configuration; |
| 220 | unsigned int central_seq_status; |
| 221 | unsigned int central_seq_option; |
| 222 | unsigned char res3[0x14]; |
| 223 | unsigned int seq_transition0; |
| 224 | unsigned int seq_transition1; |
| 225 | unsigned int seq_transition2; |
| 226 | unsigned int seq_transition3; |
| 227 | unsigned int seq_transition4; |
| 228 | unsigned int seq_transition5; |
| 229 | unsigned int seq_transition6; |
| 230 | unsigned int seq_transition7; |
| 231 | unsigned int central_seq_dmc_configuration; |
| 232 | unsigned int central_seq_dmc_status; |
| 233 | unsigned int central_seq_dmc_option; |
| 234 | unsigned char res4[0x14]; |
| 235 | unsigned int seq_dmc_transition0; |
| 236 | unsigned int seq_dmc_transition1; |
| 237 | unsigned int seq_dmc_transition2; |
| 238 | unsigned int seq_dmc_transition3; |
| 239 | unsigned int seq_dmc_transition4; |
| 240 | unsigned int seq_dmc_transition5; |
| 241 | unsigned int seq_dmc_transition6; |
| 242 | unsigned int seq_dmc_transition7; |
| 243 | unsigned char res5[0x180]; |
| 244 | unsigned int swreset; |
| 245 | unsigned int rst_stat; |
| 246 | unsigned int automatic_wdt_reset_disable; |
| 247 | unsigned int mask_wdt_reset_request; |
| 248 | unsigned int mask_wreset_request; |
| 249 | unsigned char res6[0xec]; |
| 250 | unsigned int reset_sequencer_configuration; |
| 251 | unsigned int reset_sequencer_status; |
| 252 | unsigned int reset_sequencer_option; |
| 253 | unsigned char res7[0xf4]; |
| 254 | unsigned int wakeup_stat; |
| 255 | unsigned int eint_wakeup_mask; |
| 256 | unsigned int wakeup_mask; |
| 257 | unsigned int wakeup_interrupt; |
| 258 | unsigned char res8[0x10]; |
| 259 | unsigned int wakeup_stat_dmc; |
| 260 | unsigned int eint_wakeup_mask_dmc; |
| 261 | unsigned int wakeup_mask_dmc; |
| 262 | unsigned int wakeup_interrupt_dmc; |
| 263 | unsigned char res9[0xd0]; |
| 264 | unsigned int hdmi_phy_control; |
| 265 | unsigned int usbdrd_phy_control; |
| 266 | unsigned int usbhost_phy_control; |
| 267 | unsigned int efnand_phy_control; |
| 268 | unsigned int mipi_phy0_control; |
| 269 | unsigned int mipi_phy1_control; |
| 270 | unsigned int adc_phy_control; |
| 271 | unsigned int mtcadc_phy_control; |
| 272 | unsigned int dptx_phy_control; |
| 273 | unsigned int sata_phy_control; |
| 274 | unsigned char res10[0xd8]; |
| 275 | unsigned int inform0; |
| 276 | unsigned int inform1; |
| 277 | unsigned int inform2; |
| 278 | unsigned int inform3; |
| 279 | unsigned int sysip_dat0; |
| 280 | unsigned int sysip_dat1; |
| 281 | unsigned int sysip_dat2; |
| 282 | unsigned int sysip_dat3; |
| 283 | unsigned char res11[0xe0]; |
| 284 | unsigned int pmu_spare0; |
| 285 | unsigned int pmu_spare1; |
| 286 | unsigned int pmu_spare2; |
| 287 | unsigned int pmu_spare3; |
| 288 | unsigned char res12[0x70]; |
| 289 | unsigned int irom_data_reg0; |
| 290 | unsigned int irom_data_reg1; |
| 291 | unsigned int irom_data_reg2; |
| 292 | unsigned int irom_data_reg3; |
| 293 | unsigned char res13[0x70]; |
| 294 | unsigned int pmu_debug; |
| 295 | unsigned char res14[0x5fc]; |
| 296 | unsigned int arm_core0_sys_pwr_reg; |
| 297 | unsigned int dis_irq_arm_core0_local_sys_pwr_reg; |
| 298 | unsigned int dis_irq_arm_core0_central_sys_pwr_reg; |
| 299 | unsigned char res15[0x4]; |
| 300 | unsigned int arm_core1_sys_pwr_reg; |
| 301 | unsigned int dis_irq_arm_core1_local_sys_pwr_reg; |
| 302 | unsigned int dis_irq_arm_core1_central_sys_pwr_reg; |
| 303 | unsigned char res16[0x24]; |
| 304 | unsigned int fsys_arm_sys_pwr_reg; |
| 305 | unsigned int dis_irq_fsys_arm_local_sys_pwr_reg; |
| 306 | unsigned int dis_irq_fsys_arm_central_sys_pwr_reg; |
| 307 | unsigned char res17[0x4]; |
| 308 | unsigned int isp_arm_sys_pwr_reg; |
| 309 | unsigned int dis_irq_isp_arm_local_sys_pwr_reg; |
| 310 | unsigned int dis_irq_isp_arm_central_sys_pwr_reg; |
| 311 | unsigned char res18[0x24]; |
| 312 | unsigned int arm_common_sys_pwr_reg; |
| 313 | unsigned char res19[0x3c]; |
| 314 | unsigned int arm_l2_sys_pwr_reg; |
| 315 | unsigned char res20[0x3c]; |
| 316 | unsigned int cmu_aclkstop_sys_pwr_reg; |
| 317 | unsigned int cmu_sclkstop_sys_pwr_reg; |
| 318 | unsigned char res21[0x4]; |
| 319 | unsigned int cmu_reset_sys_pwr_reg; |
| 320 | unsigned char res22[0x10]; |
| 321 | unsigned int cmu_aclkstop_dmc_sys_pwr_reg; |
| 322 | unsigned int cmu_sclkstop_dmc_sys_pwr_reg; |
| 323 | unsigned char res23[0x4]; |
| 324 | unsigned int cmu_reset_dmc_sys_pwr_reg; |
| 325 | unsigned char res24[0x8]; |
| 326 | unsigned int ddrphy_dlllock_sys_pwr_reg; |
| 327 | unsigned char res25[0x4]; |
| 328 | unsigned int apll_sysclk_sys_pwr_reg; |
| 329 | unsigned int mpll_sysclk_sys_pwr_reg; |
| 330 | unsigned int vpll_sysclk_sys_pwr_reg; |
| 331 | unsigned int epll_sysclk_sys_pwr_reg; |
| 332 | unsigned int bpll_sysclk_sys_pwr_reg; |
| 333 | unsigned int cpll_sysclk_sys_pwr_reg; |
| 334 | unsigned int gpll_sysclk_sys_pwr_reg; |
| 335 | unsigned char res26[0x8]; |
| 336 | unsigned int mplluser_sysclk_sys_pwr_reg; |
| 337 | unsigned char res27[0x8]; |
| 338 | unsigned int bplluser_sysclk_sys_pwr_reg; |
| 339 | unsigned char res28[0xc]; |
| 340 | unsigned int top_bus_sys_pwr_reg; |
| 341 | unsigned int top_retention_sys_pwr_reg; |
| 342 | unsigned int top_pwr_sys_pwr_reg; |
| 343 | unsigned char res29[0x4]; |
| 344 | unsigned int top_bus_dmc_sys_pwr_reg; |
| 345 | unsigned int top_retention_dmc_sys_pwr_reg; |
| 346 | unsigned int top_pwr_dmc_sys_pwr_reg; |
| 347 | unsigned char res30[0x4]; |
| 348 | unsigned int logic_reset_sys_pwr_reg; |
| 349 | unsigned int oscclk_gate_sys_pwr_reg; |
| 350 | unsigned char res31[0x8]; |
| 351 | unsigned int logic_reset_dmc_sys_pwr_reg; |
| 352 | unsigned int oscclk_gate_dmc_sys_pwr_reg; |
| 353 | unsigned char res32[0x8]; |
| 354 | unsigned int usbotg_mem_sys_pwr_reg; |
| 355 | unsigned char res33[0x4]; |
| 356 | unsigned int g2d_mem_sys_pwr_reg; |
| 357 | unsigned int usbdrd_mem_sys_pwr_reg; |
| 358 | unsigned int efnand_mem_sys_pwr_reg; |
| 359 | unsigned int cssys_mem_sys_pwr_reg; |
| 360 | unsigned int secss_mem_sys_pwr_reg; |
| 361 | unsigned int rotator_mem_sys_pwr_reg; |
| 362 | unsigned int intram_mem_sys_pwr_reg; |
| 363 | unsigned int introm_mem_sys_pwr_reg; |
| 364 | unsigned int jpeg_mem_sys_pwr_reg; |
| 365 | unsigned int hsi_mem_sys_pwr_reg; |
| 366 | unsigned char res34[0x4]; |
| 367 | unsigned int mcuiop_mem_sys_pwr_reg; |
| 368 | unsigned char res35[0x4]; |
| 369 | unsigned int sata_mem_sys_pwr_reg; |
| 370 | unsigned int pad_retention_dram_sys_pwr_reg; |
| 371 | unsigned int pad_retention_mau_sys_pwr_reg; |
| 372 | unsigned int pad_retention_jtag_sys_pwr_reg; |
| 373 | unsigned char res36[0xc]; |
| 374 | unsigned int pad_retention_mmc2_sys_pwr_reg; |
| 375 | unsigned int pad_retention_mmc3_sys_pwr_reg; |
| 376 | unsigned int pad_retention_gpio_sys_pwr_reg; |
| 377 | unsigned int pad_retention_uart_sys_pwr_reg; |
| 378 | unsigned int pad_retention_mmc0_sys_pwr_reg; |
| 379 | unsigned int pad_retention_mmc1_sys_pwr_reg; |
| 380 | unsigned int pad_retention_ebia_sys_pwr_reg; |
| 381 | unsigned int pad_retention_ebib_sys_pwr_reg; |
| 382 | unsigned int pad_retention_spi_sys_pwr_reg; |
| 383 | unsigned int pad_retention_gpio_dmc_sys_pwr_reg; |
| 384 | unsigned int pad_isolation_sys_pwr_reg; |
| 385 | unsigned char res37[0xc]; |
| 386 | unsigned int pad_isolation_dmc_sys_pwr_reg; |
| 387 | unsigned char res38[0xc]; |
| 388 | unsigned int pad_alv_sel_sys_pwr_reg; |
| 389 | unsigned char res39[0x20]; |
| 390 | unsigned int xxti_sys_pwr_reg; |
| 391 | unsigned char res40[0x38]; |
| 392 | unsigned int ext_regulator_sys_pwr_reg; |
| 393 | unsigned char res41[0x3c]; |
| 394 | unsigned int gpio_mode_sys_pwr_reg; |
| 395 | unsigned char res42[0x1c]; |
| 396 | unsigned int gpio_mode_dmc_sys_pwr_reg; |
| 397 | unsigned char res43[0x1c]; |
| 398 | unsigned int gpio_mode_mau_sys_pwr_reg; |
| 399 | unsigned int top_asb_reset_sys_pwr_reg; |
| 400 | unsigned int top_asb_isolation_sys_pwr_reg; |
| 401 | unsigned char res44[0xb4]; |
| 402 | unsigned int gscl_sys_pwr_reg; |
| 403 | unsigned int isp_sys_pwr_reg; |
| 404 | unsigned int mfc_sys_pwr_reg; |
| 405 | unsigned int g3d_sys_pwr_reg; |
| 406 | unsigned char res45[0x4]; |
| 407 | unsigned int disp1_sys_pwr_reg; |
| 408 | unsigned int mau_sys_pwr_reg; |
| 409 | unsigned char res46[0x64]; |
| 410 | unsigned int cmu_clkstop_gscl_sys_pwr_reg; |
| 411 | unsigned int cmu_clkstop_isp_sys_pwr_reg; |
| 412 | unsigned int cmu_clkstop_mfc_sys_pwr_reg; |
| 413 | unsigned int cmu_clkstop_g3d_sys_pwr_reg; |
| 414 | unsigned char res47[0x4]; |
| 415 | unsigned int cmu_clkstop_disp1_sys_pwr_reg; |
| 416 | unsigned int cmu_clkstop_mau_sys_pwr_reg; |
| 417 | unsigned char res48[0x24]; |
| 418 | unsigned int cmu_sysclk_gscl_sys_pwr_reg; |
| 419 | unsigned int cmu_sysclk_isp_sys_pwr_reg; |
| 420 | unsigned int cmu_sysclk_mfc_sys_pwr_reg; |
| 421 | unsigned int cmu_sysclk_g3d_sys_pwr_reg; |
| 422 | unsigned char res49[0x4]; |
| 423 | unsigned int cmu_sysclk_disp1_sys_pwr_reg; |
| 424 | unsigned int cmu_sysclk_mau_sys_pwr_reg; |
| 425 | unsigned char res50[0xa4]; |
| 426 | unsigned int cmu_reset_gscl_sys_pwr_reg; |
| 427 | unsigned int cmu_reset_isp_sys_pwr_reg; |
| 428 | unsigned int cmu_reset_mfc_sys_pwr_reg; |
| 429 | unsigned int cmu_reset_g3d_sys_pwr_reg; |
| 430 | unsigned char res51[0x4]; |
| 431 | unsigned int cmu_reset_disp1_sys_pwr_reg; |
| 432 | unsigned int cmu_reset_mau_sys_pwr_reg; |
| 433 | unsigned char res52[0xa64]; |
| 434 | unsigned int arm_core0_configuration; |
| 435 | unsigned int arm_core0_status; |
| 436 | unsigned int arm_core0_option; |
| 437 | unsigned char res53[0x14]; |
| 438 | unsigned int dis_irq_arm_core0_local_configuration; |
| 439 | unsigned int dis_irq_arm_core0_local_status; |
| 440 | unsigned int dis_irq_arm_core0_local_option; |
| 441 | unsigned char res54[0x14]; |
| 442 | unsigned int dis_irq_arm_core0_central_configuration; |
| 443 | unsigned int dis_irq_arm_core0_central_status; |
| 444 | unsigned int dis_irq_arm_core0_central_option; |
| 445 | unsigned char res55[0x34]; |
| 446 | unsigned int arm_core1_configuration; |
| 447 | unsigned int arm_core1_status; |
| 448 | unsigned int arm_core1_option; |
| 449 | unsigned char res56[0x14]; |
| 450 | unsigned int dis_irq_arm_core1_local_configuration; |
| 451 | unsigned int dis_irq_arm_core1_local_status; |
| 452 | unsigned int dis_irq_arm_core1_local_option; |
| 453 | unsigned char res57[0x14]; |
| 454 | unsigned int dis_irq_arm_core1_central_configuration; |
| 455 | unsigned int dis_irq_arm_core1_central_status; |
| 456 | unsigned int dis_irq_arm_core1_central_option; |
| 457 | unsigned char res58[0x134]; |
| 458 | unsigned int fsys_arm_configuration; |
| 459 | unsigned int fsys_arm_status; |
| 460 | unsigned int fsys_arm_option; |
| 461 | unsigned char res59[0x14]; |
| 462 | unsigned int dis_irq_fsys_arm_local_configuration; |
| 463 | unsigned int dis_irq_fsys_arm_local_status; |
| 464 | unsigned int dis_irq_fsys_arm_local_option; |
| 465 | unsigned char res60[0x14]; |
| 466 | unsigned int dis_irq_fsys_arm_central_configuration; |
| 467 | unsigned int dis_irq_fsys_arm_central_status; |
| 468 | unsigned int dis_irq_fsys_arm_central_option; |
| 469 | unsigned char res61[0x34]; |
| 470 | unsigned int isp_arm_configuration; |
| 471 | unsigned int isp_arm_status; |
| 472 | unsigned int isp_arm_option; |
| 473 | unsigned char res62[0x14]; |
| 474 | unsigned int dis_irq_isp_arm_local_configuration; |
| 475 | unsigned int dis_irq_isp_arm_local_status; |
| 476 | unsigned int dis_irq_isp_arm_local_option; |
| 477 | unsigned char res63[0x14]; |
| 478 | unsigned int dis_irq_isp_arm_central_configuration; |
| 479 | unsigned int dis_irq_isp_arm_central_status; |
| 480 | unsigned int dis_irq_isp_arm_central_option; |
| 481 | unsigned char res64[0x134]; |
| 482 | unsigned int arm_common_configuration; |
| 483 | unsigned int arm_common_status; |
| 484 | unsigned int arm_common_option; |
| 485 | unsigned char res65[0x1f4]; |
| 486 | unsigned int arm_l2_configuration; |
| 487 | unsigned int arm_l2_status; |
| 488 | unsigned int arm_l2_option; |
| 489 | unsigned char res66[0x1f4]; |
| 490 | unsigned int cmu_aclkstop_configuration; |
| 491 | unsigned int cmu_aclkstop_status; |
| 492 | unsigned int cmu_aclkstop_option; |
| 493 | unsigned char res67[0x14]; |
| 494 | unsigned int cmu_sclkstop_configuration; |
| 495 | unsigned int cmu_sclkstop_status; |
| 496 | unsigned int cmu_sclkstop_option; |
| 497 | unsigned char res68[0x34]; |
| 498 | unsigned int cmu_reset_configuration; |
| 499 | unsigned int cmu_reset_status; |
| 500 | unsigned int cmu_reset_option; |
| 501 | unsigned char res69[0x94]; |
| 502 | unsigned int cmu_aclkstop_dmc_configuration; |
| 503 | unsigned int cmu_aclkstop_dmc_status; |
| 504 | unsigned int cmu_aclkstop_dmc_option; |
| 505 | unsigned char res70[0x14]; |
| 506 | unsigned int cmu_sclkstop_dmc_configuration; |
| 507 | unsigned int cmu_sclkstop_dmc_status; |
| 508 | unsigned int cmu_sclkstop_dmc_option; |
| 509 | unsigned char res71[0x34]; |
| 510 | unsigned int cmu_reset_dmc_configuration; |
| 511 | unsigned int cmu_reset_dmc_status; |
| 512 | unsigned int cmu_reset_dmc_option; |
| 513 | unsigned char res72[0x54]; |
| 514 | unsigned int ddrphy_dlllock_configuration; |
| 515 | unsigned int ddrphy_dlllock_status; |
| 516 | unsigned int ddrphy_dlllock_option; |
| 517 | unsigned char res73[0x34]; |
| 518 | unsigned int apll_sysclk_configuration; |
| 519 | unsigned int apll_sysclk_status; |
| 520 | unsigned int apll_sysclk_option; |
| 521 | unsigned char res74[0x18]; |
| 522 | unsigned int mpll_sysclk_status; |
| 523 | unsigned int mpll_sysclk_option; |
| 524 | unsigned char res75[0x14]; |
| 525 | unsigned int vpll_sysclk_configuration; |
| 526 | unsigned int vpll_sysclk_status; |
| 527 | unsigned int vpll_sysclk_option; |
| 528 | unsigned char res76[0x14]; |
| 529 | unsigned int epll_sysclk_configuration; |
| 530 | unsigned int epll_sysclk_status; |
| 531 | unsigned int epll_sysclk_option; |
| 532 | unsigned char res77[0x14]; |
| 533 | unsigned int bpll_sysclk_configuration; |
| 534 | unsigned int bpll_sysclk_status; |
| 535 | unsigned int bpll_sysclk_option; |
| 536 | unsigned char res78[0x14]; |
| 537 | unsigned int cpll_sysclk_configuration; |
| 538 | unsigned int cpll_sysclk_status; |
| 539 | unsigned int cpll_sysclk_option; |
| 540 | unsigned char res79[0x14]; |
| 541 | unsigned int gpll_sysclk_configuration; |
| 542 | unsigned int gpll_sysclk_status; |
| 543 | unsigned int gpll_sysclk_option; |
| 544 | unsigned char res80[0x54]; |
| 545 | unsigned int mplluser_sysclk_configuration; |
| 546 | unsigned int mplluser_sysclk_status; |
| 547 | unsigned int mplluser_sysclk_option; |
| 548 | unsigned char res81[0x54]; |
| 549 | unsigned int bplluser_sysclk_configuration; |
| 550 | unsigned int bplluser_sysclk_status; |
| 551 | unsigned int bplluser_sysclk_option; |
| 552 | unsigned char res82[0x74]; |
| 553 | unsigned int top_bus_configuration; |
| 554 | unsigned int top_bus_status; |
| 555 | unsigned int top_bus_option; |
| 556 | unsigned char res83[0x14]; |
| 557 | unsigned int top_retention_configuration; |
| 558 | unsigned int top_retention_status; |
| 559 | unsigned int top_retention_option; |
| 560 | unsigned char res84[0x14]; |
| 561 | unsigned int top_pwr_configuration; |
| 562 | unsigned int top_pwr_status; |
| 563 | unsigned int top_pwr_option; |
| 564 | unsigned char res85[0x34]; |
| 565 | unsigned int top_bus_dmc_configuration; |
| 566 | unsigned int top_bus_dmc_status; |
| 567 | unsigned int top_bus_dmc_option; |
| 568 | unsigned char res86[0x14]; |
| 569 | unsigned int top_retention_dmc_configuration; |
| 570 | unsigned int top_retention_dmc_status; |
| 571 | unsigned int top_retention_dmc_option; |
| 572 | unsigned char res87[0x14]; |
| 573 | unsigned int top_pwr_dmc_configuration; |
| 574 | unsigned int top_pwr_dmc_status; |
| 575 | unsigned int top_pwr_dmc_option; |
| 576 | unsigned char res88[0x34]; |
| 577 | unsigned int logic_reset_configuration; |
| 578 | unsigned int logic_reset_status; |
| 579 | unsigned int logic_reset_option; |
| 580 | unsigned char res89[0x14]; |
| 581 | unsigned int oscclk_gate_configuration; |
| 582 | unsigned int oscclk_gate_status; |
| 583 | unsigned int oscclk_gate_option; |
| 584 | unsigned char res90[0x54]; |
| 585 | unsigned int logic_reset_dmc_configuration; |
| 586 | unsigned int logic_reset_dmc_status; |
| 587 | unsigned int logic_reset_dmc_option; |
| 588 | unsigned char res91[0x14]; |
| 589 | unsigned int oscclk_gate_dmc_configuration; |
| 590 | unsigned int oscclk_gate_dmc_status; |
| 591 | unsigned int oscclk_gate_dmc_option; |
| 592 | unsigned char res92[0x54]; |
| 593 | unsigned int usbotg_mem_configuration; |
| 594 | unsigned int usbotg_mem_status; |
| 595 | unsigned int usbotg_mem_option; |
| 596 | unsigned char res93[0x34]; |
| 597 | unsigned int g2d_mem_configuration; |
| 598 | unsigned int g2d_mem_status; |
| 599 | unsigned int g2d_mem_option; |
| 600 | unsigned char res94[0x14]; |
| 601 | unsigned int usbdrd_mem_configuration; |
| 602 | unsigned int usbdrd_mem_status; |
| 603 | unsigned int usbdrd_mem_option; |
| 604 | unsigned char res95[0x14]; |
| 605 | unsigned int efnand_mem_configuration; |
| 606 | unsigned int efnand_mem_status; |
| 607 | unsigned int efnand_mem_option; |
| 608 | unsigned char res96[0x14]; |
| 609 | unsigned int cssys_mem_configuration; |
| 610 | unsigned int cssys_mem_status; |
| 611 | unsigned int cssys_mem_option; |
| 612 | unsigned char res97[0x14]; |
| 613 | unsigned int secss_mem_configuration; |
| 614 | unsigned int secss_mem_status; |
| 615 | unsigned int secss_mem_option; |
| 616 | unsigned char res98[0x14]; |
| 617 | unsigned int rotator_mem_configuration; |
| 618 | unsigned int rotator_mem_status; |
| 619 | unsigned int rotator_mem_option; |
| 620 | unsigned char res99[0x14]; |
| 621 | unsigned int intram_mem_configuration; |
| 622 | unsigned int intram_mem_status; |
| 623 | unsigned int intram_mem_option; |
| 624 | unsigned char res100[0x14]; |
| 625 | unsigned int introm_mem_configuration; |
| 626 | unsigned int introm_mem_status; |
| 627 | unsigned int introm_mem_option; |
| 628 | unsigned char res101[0x14]; |
| 629 | unsigned int jpeg_mem_configuration; |
| 630 | unsigned int jpeg_mem_status; |
| 631 | unsigned int jpeg_mem_option; |
| 632 | unsigned char res102[0x14]; |
| 633 | unsigned int hsi_mem_configuration; |
| 634 | unsigned int hsi_mem_status; |
| 635 | unsigned int hsi_mem_option; |
| 636 | unsigned char res103[0x34]; |
| 637 | unsigned int mcuiop_mem_configuration; |
| 638 | unsigned int mcuiop_mem_status; |
| 639 | unsigned int mcuiop_mem_option; |
| 640 | unsigned char res104[0x14]; |
| 641 | unsigned int sata_mem_configuration; |
| 642 | unsigned int sata_mem_status; |
| 643 | unsigned int sata_mem_option; |
| 644 | unsigned char res105[0x34]; |
| 645 | unsigned int pad_retention_dram_configuration; |
| 646 | unsigned int pad_retention_dram_status; |
| 647 | unsigned int pad_retention_dram_option; |
| 648 | unsigned char res106[0x14]; |
| 649 | unsigned int pad_retention_mau_configuration; |
| 650 | unsigned int pad_retention_mau_status; |
| 651 | unsigned int pad_retention_mau_option; |
| 652 | unsigned char res107[0x14]; |
| 653 | unsigned int pad_retention_jtag_configuration; |
| 654 | unsigned int pad_retention_jtag_status; |
| 655 | unsigned int pad_retention_jtag_option; |
| 656 | unsigned char res108[0x74]; |
| 657 | unsigned int pad_retention_mmc2_configuration; |
| 658 | unsigned int pad_retention_mmc2_status; |
| 659 | unsigned int pad_retention_mmc2_option; |
| 660 | unsigned char res109[0x14]; |
| 661 | unsigned int pad_retention_mmc3_configuration; |
| 662 | unsigned int pad_retention_mmc3_status; |
| 663 | unsigned int pad_retention_mmc3_option; |
| 664 | unsigned char res110[0x14]; |
| 665 | unsigned int pad_retention_gpio_configuration; |
| 666 | unsigned int pad_retention_gpio_status; |
| 667 | unsigned int pad_retention_gpio_option; |
| 668 | unsigned char res111[0x14]; |
| 669 | unsigned int pad_retention_uart_configuration; |
| 670 | unsigned int pad_retention_uart_status; |
| 671 | unsigned int pad_retention_uart_option; |
| 672 | unsigned char res112[0x14]; |
| 673 | unsigned int pad_retention_mmc0_configuration; |
| 674 | unsigned int pad_retention_mmc0_status; |
| 675 | unsigned int pad_retention_mmc0_option; |
| 676 | unsigned char res113[0x14]; |
| 677 | unsigned int pad_retention_mmc1_configuration; |
| 678 | unsigned int pad_retention_mmc1_status; |
| 679 | unsigned int pad_retention_mmc1_option; |
| 680 | unsigned char res114[0x14]; |
| 681 | unsigned int pad_retention_ebia_configuration; |
| 682 | unsigned int pad_retention_ebia_status; |
| 683 | unsigned int pad_retention_ebia_option; |
| 684 | unsigned char res115[0x14]; |
| 685 | unsigned int pad_retention_ebib_configuration; |
| 686 | unsigned int pad_retention_ebib_status; |
| 687 | unsigned int pad_retention_ebib_option; |
| 688 | unsigned char res116[0x14]; |
| 689 | unsigned int pad_retention_spi_configuration; |
| 690 | unsigned int pad_retention_spi_status; |
| 691 | unsigned int pad_retention_spi_option; |
| 692 | unsigned char res117[0x14]; |
| 693 | unsigned int pad_retention_gpio_dmc_configuration; |
| 694 | unsigned int pad_retention_gpio_dmc_status; |
| 695 | unsigned int pad_retention_gpio_dmc_option; |
| 696 | unsigned char res118[0x14]; |
| 697 | unsigned int pad_isolation_configuration; |
| 698 | unsigned int pad_isolation_status; |
| 699 | unsigned int pad_isolation_option; |
| 700 | unsigned char res119[0x74]; |
| 701 | unsigned int pad_isolation_dmc_configuration; |
| 702 | unsigned int pad_isolation_dmc_status; |
| 703 | unsigned int pad_isolation_dmc_option; |
| 704 | unsigned char res120[0x74]; |
| 705 | unsigned int pad_alv_sel_configuration; |
| 706 | unsigned int pad_alv_sel_status; |
| 707 | unsigned int pad_alv_sel_option0; |
| 708 | unsigned int ps_hold_control; |
| 709 | unsigned char res130[0x110]; |
| 710 | unsigned int xxti_configuration; |
| 711 | unsigned int xxti_status; |
| 712 | unsigned int xxti_option; |
| 713 | unsigned char res131[0x10]; |
| 714 | unsigned int xxti_duration3; |
| 715 | unsigned char res132[0x1c0]; |
| 716 | unsigned int ext_regulator_configuration; |
| 717 | unsigned int ext_regulator_status; |
| 718 | unsigned int ext_regulator_option; |
| 719 | unsigned char res133[0x10]; |
| 720 | unsigned int ext_regulator_duration3; |
| 721 | unsigned char res134[0x1e0]; |
| 722 | unsigned int gpio_mode_configuration; |
| 723 | unsigned int gpio_mode_status; |
| 724 | unsigned int gpio_mode_option; |
| 725 | unsigned char res135[0xf4]; |
| 726 | unsigned int gpio_mode_dmc_configuration; |
| 727 | unsigned int gpio_mode_dmc_status; |
| 728 | unsigned int gpio_mode_dmc_option; |
| 729 | unsigned char res136[0xd4]; |
| 730 | unsigned int gpio_mode_mau_configuration; |
| 731 | unsigned int gpio_mode_mau_status; |
| 732 | unsigned int gpio_mode_mau_option; |
| 733 | unsigned char res137[0x14]; |
| 734 | unsigned int top_asb_reset_configuration; |
| 735 | unsigned int top_asb_reset_status; |
| 736 | unsigned int top_asb_reset_option; |
| 737 | unsigned char res138[0x14]; |
| 738 | unsigned int top_asb_isolation_configuration; |
| 739 | unsigned int top_asb_isolation_status; |
| 740 | unsigned int top_asb_isolation_option; |
| 741 | unsigned char res139[0x5d4]; |
| 742 | unsigned int gscl_configuration; |
| 743 | unsigned int gscl_status; |
| 744 | unsigned int gscl_option; |
| 745 | unsigned char res140[0x14]; |
| 746 | unsigned int isp_configuration; |
| 747 | unsigned int isp_status; |
| 748 | unsigned int isp_option; |
| 749 | unsigned char res141[0x14]; |
| 750 | unsigned int mfc_configuration; |
| 751 | unsigned int mfc_status; |
| 752 | unsigned int mfc_option; |
| 753 | unsigned char res142[0x14]; |
| 754 | unsigned int g3d_configuration; |
| 755 | unsigned int g3d_status; |
| 756 | unsigned int g3d_option; |
| 757 | unsigned char res143[0x34]; |
| 758 | unsigned int disp1_configuration; |
| 759 | unsigned int disp1_status; |
| 760 | unsigned int disp1_option; |
| 761 | unsigned char res144[0x14]; |
| 762 | unsigned int mau_configuration; |
| 763 | unsigned int mau_status; |
| 764 | unsigned int mau_option; |
| 765 | unsigned char res145[0x334]; |
| 766 | unsigned int cmu_clkstop_gscl_configuration; |
| 767 | unsigned int cmu_clkstop_gscl_status; |
| 768 | unsigned int cmu_clkstop_gscl_option; |
| 769 | unsigned char res146[0x14]; |
| 770 | unsigned int cmu_clkstop_isp_configuration; |
| 771 | unsigned int cmu_clkstop_isp_status; |
| 772 | unsigned int cmu_clkstop_isp_option; |
| 773 | unsigned char res147[0x14]; |
| 774 | unsigned int cmu_clkstop_mfc_configuration; |
| 775 | unsigned int cmu_clkstop_mfc_status; |
| 776 | unsigned int cmu_clkstop_mfc_option; |
| 777 | unsigned char res148[0x14]; |
| 778 | unsigned int cmu_clkstop_g3d_configuration; |
| 779 | unsigned int cmu_clkstop_g3d_status; |
| 780 | unsigned int cmu_clkstop_g3d_option; |
| 781 | unsigned char res149[0x34]; |
| 782 | unsigned int cmu_clkstop_disp1_configuration; |
| 783 | unsigned int cmu_clkstop_disp1_status; |
| 784 | unsigned int cmu_clkstop_disp1_option; |
| 785 | unsigned char res150[0x14]; |
| 786 | unsigned int cmu_clkstop_mau_configuration; |
| 787 | unsigned int cmu_clkstop_mau_status; |
| 788 | unsigned int cmu_clkstop_mau_option; |
| 789 | unsigned char res151[0x134]; |
| 790 | unsigned int cmu_sysclk_gscl_configuration; |
| 791 | unsigned int cmu_sysclk_gscl_status; |
| 792 | unsigned int cmu_sysclk_gscl_option; |
| 793 | unsigned char res152[0x18]; |
| 794 | unsigned int cmu_sysclk_isp_status; |
| 795 | unsigned int cmu_sysclk_isp_option; |
| 796 | unsigned char res153[0x18]; |
| 797 | unsigned int cmu_sysclk_mfc_status; |
| 798 | unsigned int cmu_sysclk_mfc_option; |
| 799 | unsigned char res154[0x18]; |
| 800 | unsigned int cmu_sysclk_g3d_status; |
| 801 | unsigned int cmu_sysclk_g3d_option; |
| 802 | unsigned char res155[0x38]; |
| 803 | unsigned int cmu_sysclk_disp1_status; |
| 804 | unsigned int cmu_sysclk_disp1_option; |
| 805 | unsigned char res156[0x18]; |
| 806 | unsigned int cmu_sysclk_mau_status; |
| 807 | unsigned int cmu_sysclk_mau_option; |
| 808 | unsigned char res157[0x534]; |
| 809 | unsigned int cmu_reset_gscl_configuration; |
| 810 | unsigned int cmu_reset_gscl_status; |
| 811 | unsigned int cmu_reset_gscl_option; |
| 812 | unsigned char res158[0x14]; |
| 813 | unsigned int cmu_reset_isp_configuration; |
| 814 | unsigned int cmu_reset_isp_status; |
| 815 | unsigned int cmu_reset_isp_option; |
| 816 | unsigned char res159[0x14]; |
| 817 | unsigned int cmu_reset_mfc_configuration; |
| 818 | unsigned int cmu_reset_mfc_status; |
| 819 | unsigned int cmu_reset_mfc_option; |
| 820 | unsigned char res160[0x14]; |
| 821 | unsigned int cmu_reset_g3d_configuration; |
| 822 | unsigned int cmu_reset_g3d_status; |
| 823 | unsigned int cmu_reset_g3d_option; |
| 824 | unsigned char res161[0x34]; |
| 825 | unsigned int cmu_reset_disp1_configuration; |
| 826 | unsigned int cmu_reset_disp1_status; |
| 827 | unsigned int cmu_reset_disp1_option; |
| 828 | unsigned char res162[0x14]; |
| 829 | unsigned int cmu_reset_mau_configuration; |
| 830 | unsigned int cmu_reset_mau_status; |
| 831 | unsigned int cmu_reset_mau_option; |
| 832 | unsigned char res163[0x24]; |
| 833 | }; |
| HeungJun, Kim | b371727 | 2012-01-16 21:13:04 +0000 | [diff] [blame] | 834 | #endif /* __ASSEMBLY__ */ |
| 835 | |
| Donghwa Lee | 0955271 | 2012-04-05 19:36:10 +0000 | [diff] [blame] | 836 | void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); |
| 837 | |
| 838 | #define EXYNOS_MIPI_PHY_ENABLE (1 << 0) |
| 839 | #define EXYNOS_MIPI_PHY_SRESETN (1 << 1) |
| 840 | #define EXYNOS_MIPI_PHY_MRESETN (1 << 2) |
| 841 | |
| Rajeshwari Shinde | 21965ac | 2012-05-14 05:52:03 +0000 | [diff] [blame] | 842 | void set_usbhost_phy_ctrl(unsigned int enable); |
| 843 | |
| Akshay Saraswat | b9fa8c1 | 2013-02-25 01:13:06 +0000 | [diff] [blame] | 844 | /* Enables hardware tripping to power off the system when TMU fails */ |
| 845 | void set_hw_thermal_trip(void); |
| 846 | |
| Rajeshwari Shinde | 21965ac | 2012-05-14 05:52:03 +0000 | [diff] [blame] | 847 | #define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) |
| 848 | #define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) |
| Donghwa Lee | a6b453f | 2012-07-02 01:15:56 +0000 | [diff] [blame] | 849 | |
| Vivek Gautam | 4e16e2f | 2013-09-14 14:02:47 +0530 | [diff] [blame^] | 850 | void set_usbdrd_phy_ctrl(unsigned int enable); |
| 851 | |
| 852 | #define POWER_USB_DRD_PHY_CTRL_EN (1 << 0) |
| 853 | #define POWER_USB_DRD_PHY_CTRL_DISABLE (0 << 0) |
| 854 | |
| Donghwa Lee | a6b453f | 2012-07-02 01:15:56 +0000 | [diff] [blame] | 855 | void set_dp_phy_ctrl(unsigned int enable); |
| 856 | |
| 857 | #define EXYNOS_DP_PHY_ENABLE (1 << 0) |
| 858 | |
| Rajeshwari Shinde | 6c4e99b | 2013-02-12 20:40:01 +0000 | [diff] [blame] | 859 | #define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH (1 << 8) |
| Akshay Saraswat | b9fa8c1 | 2013-02-25 01:13:06 +0000 | [diff] [blame] | 860 | #define POWER_ENABLE_HW_TRIP (1UL << 31) |
| Rajeshwari Shinde | 6c4e99b | 2013-02-12 20:40:01 +0000 | [diff] [blame] | 861 | |
| 862 | /* |
| 863 | * Set ps_hold data driving value high |
| 864 | * This enables the machine to stay powered on |
| 865 | * after the initial power-on condition goes away |
| 866 | * (e.g. power button). |
| 867 | */ |
| 868 | void set_ps_hold_ctrl(void); |
| Rajeshwari Shinde | 73de8d6 | 2013-02-14 19:46:11 +0000 | [diff] [blame] | 869 | |
| 870 | /* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ |
| 871 | #define PMU_DEBUG_XXTI 0x1000 |
| 872 | /* Mask bit[12:8] for xxti clock selection */ |
| 873 | #define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 |
| 874 | |
| 875 | /* |
| 876 | * Pmu debug is used for xclkout, enable xclkout with |
| 877 | * source as XXTI |
| 878 | */ |
| 879 | void set_xclkout(void); |
| Rajeshwari Shinde | 33dcbd2 | 2013-07-04 12:29:14 +0530 | [diff] [blame] | 880 | |
| 881 | /* |
| 882 | * Read inform1 to get the reset status. |
| 883 | * @return: the value can be either S5P_CHECK_SLEEP or |
| 884 | * S5P_CHECK_DIDLE or S5P_CHECK_LPA as stored in inform1 |
| 885 | * if none of these then its normal booting. |
| 886 | */ |
| 887 | uint32_t get_reset_status(void); |
| 888 | |
| 889 | |
| 890 | /* Read the resume function and call it */ |
| 891 | void power_exit_wakeup(void); |
| HeungJun, Kim | b371727 | 2012-01-16 21:13:04 +0000 | [diff] [blame] | 892 | #endif |