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Graeme Russa875dda2011-12-23 16:51:29 +11001/*
2 * (C) Copyright 2011
3 * Graeme Russ, <graeme.russ@gmail.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Graeme Russa875dda2011-12-23 16:51:29 +11006 */
7#include <common.h>
Simon Glass347c05b2013-02-28 19:26:15 +00008#include <fdtdec.h>
Gabe Blacka97cbda2012-11-03 11:41:23 +00009#include <spi.h>
Bin Meng80d29762015-01-22 11:29:41 +080010#include <asm/errno.h>
Simon Glass004ba172015-01-01 16:18:11 -070011#include <asm/mtrr.h>
Simon Glass3e93e332013-03-05 14:39:54 +000012#include <asm/sections.h>
Graeme Russa875dda2011-12-23 16:51:29 +110013
14DECLARE_GLOBAL_DATA_PTR;
15
Simon Glass3297d4d2013-02-28 19:26:10 +000016/* Get the top of usable RAM */
17__weak ulong board_get_usable_ram_top(ulong total_size)
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110018{
Simon Glass3297d4d2013-02-28 19:26:10 +000019 return gd->ram_size;
20}
21
22int calculate_relocation_address(void)
23{
24 const ulong uboot_size = (uintptr_t)&__bss_end -
25 (uintptr_t)&__text_start;
26 ulong total_size;
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110027 ulong dest_addr;
Simon Glass347c05b2013-02-28 19:26:15 +000028 ulong fdt_size = 0;
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110029
Simon Glass347c05b2013-02-28 19:26:15 +000030#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
31 if (gd->fdt_blob)
32 fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
33#endif
Simon Glass3297d4d2013-02-28 19:26:10 +000034 total_size = ALIGN(uboot_size, 1 << 12) + CONFIG_SYS_MALLOC_LEN +
Simon Glass347c05b2013-02-28 19:26:15 +000035 CONFIG_SYS_STACK_SIZE + fdt_size;
Simon Glass3297d4d2013-02-28 19:26:10 +000036
Simon Glass347c05b2013-02-28 19:26:15 +000037 dest_addr = board_get_usable_ram_top(total_size);
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110038 /*
39 * NOTE: All destination address are rounded down to 16-byte
40 * boundary to satisfy various worst-case alignment
41 * requirements
42 */
Simon Glass347c05b2013-02-28 19:26:15 +000043 dest_addr &= ~15;
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110044
Simon Glass347c05b2013-02-28 19:26:15 +000045#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
46 /*
47 * If the device tree is sitting immediate above our image then we
48 * must relocate it. If it is embedded in the data section, then it
49 * will be relocated with other data.
50 */
51 if (gd->fdt_blob) {
52 dest_addr -= fdt_size;
Simon Glassc45e3592013-03-11 06:49:53 +000053 gd->new_fdt = (void *)dest_addr;
Simon Glass347c05b2013-02-28 19:26:15 +000054 dest_addr &= ~15;
55 }
56#endif
Simon Glass3297d4d2013-02-28 19:26:10 +000057 /* U-Boot is below the FDT */
58 dest_addr -= uboot_size;
59 dest_addr &= ~((1 << 12) - 1);
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110060 gd->relocaddr = dest_addr;
Simon Glass3297d4d2013-02-28 19:26:10 +000061 gd->reloc_off = dest_addr - (uintptr_t)&__text_start;
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110062
Gabe Black13113612012-11-03 11:41:24 +000063 /* Stack is at the bottom, so it can grow down */
64 gd->start_addr_sp = dest_addr - CONFIG_SYS_MALLOC_LEN;
65
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110066 return 0;
67}
68
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110069int init_cache_f_r(void)
70{
Simon Glass004ba172015-01-01 16:18:11 -070071#if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP)
72 int ret;
73
74 ret = mtrr_commit(false);
Bin Meng80d29762015-01-22 11:29:41 +080075 /* If MTRR MSR is not implemented by the processor, just ignore it */
76 if (ret && ret != -ENOSYS)
Simon Glass004ba172015-01-01 16:18:11 -070077 return ret;
78#endif
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110079 /* Initialise the CPU cache(s) */
80 return init_cache();
81}
82
Graeme Russa875dda2011-12-23 16:51:29 +110083bd_t bd_data;
84
85int init_bd_struct_r(void)
86{
87 gd->bd = &bd_data;
88 memset(gd->bd, 0, sizeof(bd_t));
89
90 return 0;
91}
92
Gabe Blacka97cbda2012-11-03 11:41:23 +000093int init_func_spi(void)
94{
95 puts("SPI: ");
96 spi_init();
97 puts("ready\n");
98 return 0;
99}