blob: 35735f3b78e48433438112b1f47fe2d398593f98 [file] [log] [blame]
Tom Warren22425c92015-02-12 15:01:49 -07001/*
2 * (C) Copyright 2013-2015
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _TEGRA210_COMMON_H_
9#define _TEGRA210_COMMON_H_
10
11#include "tegra-common.h"
12
Tom Warren22425c92015-02-12 15:01:49 -070013/*
14 * NS16550 Configuration
15 */
16#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
17
Tom Warren22425c92015-02-12 15:01:49 -070018/*-----------------------------------------------------------------------
19 * Physical Memory Map
20 */
Stephen Warrenf5bd7452015-09-23 12:34:01 -060021#define CONFIG_SYS_TEXT_BASE 0x80110000
Tom Warren22425c92015-02-12 15:01:49 -070022
23/* Generic Interrupt Controller */
24#define CONFIG_GICV2
25
26/*
27 * Memory layout for where various images get loaded by boot scripts:
28 *
29 * scriptaddr can be pretty much anywhere that doesn't conflict with something
30 * else. Put it above BOOTMAPSZ to eliminate conflicts.
31 *
32 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
33 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
34 *
35 * kernel_addr_r must be within the first 128M of RAM in order for the
36 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
37 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
38 * should not overlap that area, or the kernel will have to copy itself
39 * somewhere else before decompression. Similarly, the address of any other
40 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
41 * this up to 16M allows for a sizable kernel to be decompressed below the
42 * compressed load address.
43 *
44 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
45 * the compressed kernel to be up to 16M too.
46 *
47 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
48 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
49 */
Stephen Warren5eed1a52015-08-07 16:12:43 -060050#define CONFIG_LOADADDR 0x80080000
Tom Warren22425c92015-02-12 15:01:49 -070051#define MEM_LAYOUT_ENV_SETTINGS \
52 "scriptaddr=0x90000000\0" \
53 "pxefile_addr_r=0x90100000\0" \
54 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
55 "fdt_addr_r=0x82000000\0" \
56 "ramdisk_addr_r=0x82100000\0"
57
Tom Warren22425c92015-02-12 15:01:49 -070058/* For USB EHCI controller */
59#define CONFIG_EHCI_IS_TDI
60#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
Tom Warren22425c92015-02-12 15:01:49 -070061
Alexandre Courbot7f936d42015-07-09 16:33:00 +090062/* GPU needs setup */
63#define CONFIG_TEGRA_GPU
64
Tom Warren22425c92015-02-12 15:01:49 -070065#endif /* _TEGRA210_COMMON_H_ */