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git01.mediatek.com / filogic / uboot / 4df43d4f3964a9baffdabf62685c4db3d885ded2 / . / include / configs / stout.h
blob: 789f364168d928d49d1a544750f5a54603a52abd [file] [log] [blame]
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]1/*
2 * include/configs/stout.h
3 * This file is Stout board configuration.
4 *
5 * Copyright (C) 2015 Renesas Electronics Europe GmbH
6 * Copyright (C) 2015 Renesas Electronics Corporation
7 * Copyright (C) 2015 Cogent Embedded, Inc.
8 *
9 * SPDX-License-Identifier: GPL-2.0
10 */
11
12#ifndef __STOUT_H
13#define __STOUT_H
14
15#undef DEBUG
16#define CONFIG_R8A7790
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +0900[diff] [blame]17#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Stout"
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]18
19#include "rcar-gen2-common.h"
20
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +0900[diff] [blame]21#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]22#define CONFIG_SYS_TEXT_BASE 0xB0000000
23#else
24#define CONFIG_SYS_TEXT_BASE 0xE8080000
25#endif
26
27/* STACK */
28#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
29#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
30#else
31#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
32#endif
33#define STACK_AREA_SIZE 0xC000
34#define LOW_LEVEL_MERAM_STACK \
35 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
36
37/* MEMORY */
38#define RCAR_GEN2_SDRAM_BASE 0x40000000
39#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
40#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
41
42/* SCIF */
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]43#define CONFIG_SCIF_A
44
45/* SPI */
46#define CONFIG_SPI
47#define CONFIG_SH_QSPI
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]48#define CONFIG_SPI_FLASH_QUAD
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]49
50/* SH Ether */
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]51#define CONFIG_SH_ETHER_USE_PORT 0
52#define CONFIG_SH_ETHER_PHY_ADDR 0x1
53#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
54#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
55#define CONFIG_SH_ETHER_CACHE_WRITEBACK
56#define CONFIG_SH_ETHER_CACHE_INVALIDATE
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]57#define CONFIG_BITBANGMII
58#define CONFIG_BITBANGMII_MULTI
59
60/* I2C */
61#define CONFIG_SYS_I2C
62#define CONFIG_SYS_I2C_RCAR
63#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
64#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
65#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
66#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
67#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
68
69#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
70
71/* Board Clock */
72#define RMOBILE_XTAL_CLK 20000000u
73#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
74#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
75#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
76#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
77#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
78#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
79
80#define CONFIG_SYS_TMU_CLK_DIV 4
81
82/* USB */
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]83#define CONFIG_USB_EHCI_RMOBILE
84#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]85
Vladimir Barinov8c946272015-07-20 20:49:59 +0300[diff] [blame]86/* Module stop status bits */
87/* INTC-RT */
88#define CONFIG_SMSTP0_ENA 0x00400000
89/* MSIF, SCIFA0 */
90#define CONFIG_SMSTP2_ENA 0x00002010
91/* INTC-SYS, IRQC */
92#define CONFIG_SMSTP4_ENA 0x00000180
93
94/* SDHI */
95#define CONFIG_SH_SDHI_FREQ 97500000
96
97#endif /* __STOUT_H */