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git01.mediatek.com / filogic / uboot / 4de44bbc0b6a5595cb2acdb93f478cb99934e29e / . / drivers / clk / imx / clk-imx6q.c
blob: 92e9337d4464b1b00f420a5d875d8d1fe1f32fda [file] [log] [blame]
Lukasz Majewski4de44bb2019-06-24 15:50:45 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/imx-regs.h>
12#include <dt-bindings/clock/imx6qdl-clock.h>
13
14#include "clk.h"
15
16static int imx6q_check_id(ulong id)
17{
18 if (id < IMX6QDL_CLK_DUMMY || id >= IMX6QDL_CLK_END) {
19 printf("%s: Invalid clk ID #%lu\n", __func__, id);
20 return -EINVAL;
21 }
22
23 return 0;
24}
25
26static ulong imx6q_clk_get_rate(struct clk *clk)
27{
28 struct clk *c;
29 int ret;
30
31 debug("%s(#%lu)\n", __func__, clk->id);
32
33 ret = imx6q_check_id(clk->id);
34 if (ret)
35 return ret;
36
37 ret = clk_get_by_id(clk->id, &c);
38 if (ret)
39 return ret;
40
41 return clk_get_rate(c);
42}
43
44static ulong imx6q_clk_set_rate(struct clk *clk, unsigned long rate)
45{
46 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
47
48 return rate;
49}
50
51static int __imx6q_clk_enable(struct clk *clk, bool enable)
52{
53 struct clk *c;
54 int ret = 0;
55
56 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
57
58 ret = imx6q_check_id(clk->id);
59 if (ret)
60 return ret;
61
62 ret = clk_get_by_id(clk->id, &c);
63 if (ret)
64 return ret;
65
66 if (enable)
67 ret = clk_enable(c);
68 else
69 ret = clk_disable(c);
70
71 return ret;
72}
73
74static int imx6q_clk_disable(struct clk *clk)
75{
76 return __imx6q_clk_enable(clk, 0);
77}
78
79static int imx6q_clk_enable(struct clk *clk)
80{
81 return __imx6q_clk_enable(clk, 1);
82}
83
84static struct clk_ops imx6q_clk_ops = {
85 .set_rate = imx6q_clk_set_rate,
86 .get_rate = imx6q_clk_get_rate,
87 .enable = imx6q_clk_enable,
88 .disable = imx6q_clk_disable,
89};
90
91static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
92
93static int imx6q_clk_probe(struct udevice *dev)
94{
95 void *base;
96
97 /* Anatop clocks */
98 base = (void *)ANATOP_BASE_ADDR;
99
100 clk_dm(IMX6QDL_CLK_PLL2,
101 imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
102 base + 0x30, 0x1));
103 clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
104 imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
105 base + 0x10, 0x3));
106 clk_dm(IMX6QDL_CLK_PLL3_60M,
107 imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
108 clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
109 imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
110 clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
111 imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
112
113 /* CCM clocks */
114 base = dev_read_addr_ptr(dev);
115 if (base == (void *)FDT_ADDR_T_NONE)
116 return -EINVAL;
117
118 clk_dm(IMX6QDL_CLK_USDHC1_SEL,
119 imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
120 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
121 clk_dm(IMX6QDL_CLK_USDHC2_SEL,
122 imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
123 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
124 clk_dm(IMX6QDL_CLK_USDHC3_SEL,
125 imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
126 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
127 clk_dm(IMX6QDL_CLK_USDHC4_SEL,
128 imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
129 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
130
131 clk_dm(IMX6QDL_CLK_USDHC1_PODF,
132 imx_clk_divider("usdhc1_podf", "usdhc1_sel",
133 base + 0x24, 11, 3));
134 clk_dm(IMX6QDL_CLK_USDHC2_PODF,
135 imx_clk_divider("usdhc2_podf", "usdhc2_sel",
136 base + 0x24, 16, 3));
137 clk_dm(IMX6QDL_CLK_USDHC3_PODF,
138 imx_clk_divider("usdhc3_podf", "usdhc3_sel",
139 base + 0x24, 19, 3));
140 clk_dm(IMX6QDL_CLK_USDHC4_PODF,
141 imx_clk_divider("usdhc4_podf", "usdhc4_sel",
142 base + 0x24, 22, 3));
143
144 clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
145 imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
146
147 clk_dm(IMX6QDL_CLK_ECSPI1,
148 imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
149 clk_dm(IMX6QDL_CLK_ECSPI2,
150 imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
151 clk_dm(IMX6QDL_CLK_ECSPI3,
152 imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
153 clk_dm(IMX6QDL_CLK_ECSPI4,
154 imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
155 clk_dm(IMX6QDL_CLK_USDHC1,
156 imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
157 clk_dm(IMX6QDL_CLK_USDHC2,
158 imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
159 clk_dm(IMX6QDL_CLK_USDHC3,
160 imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
161 clk_dm(IMX6QDL_CLK_USDHC4,
162 imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
163
164 return 0;
165}
166
167static const struct udevice_id imx6q_clk_ids[] = {
168 { .compatible = "fsl,imx6q-ccm" },
169 { },
170};
171
172U_BOOT_DRIVER(imx6q_clk) = {
173 .name = "clk_imx6q",
174 .id = UCLASS_CLK,
175 .of_match = imx6q_clk_ids,
176 .ops = &imx6q_clk_ops,
177 .probe = imx6q_clk_probe,
178 .flags = DM_FLAG_PRE_RELOC,
179};