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git01.mediatek.com / filogic / uboot / 4de11284816cf5e3521fe17f880386aa1a57afd7 / . / configs / rock64-rk3328_defconfig
blob: 6704946c16c0a07b887da83f446bfdc1b1edc707 [file] [log] [blame]
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]3CONFIG_ARCH_ROCKCHIP=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]4CONFIG_SYS_TEXT_BASE=0x00200000
Simon Glass035939e2021-07-10 21:14:30 -0600[diff] [blame]5CONFIG_SPL_GPIO=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=1
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]7CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]9CONFIG_ROCKCHIP_RK3328=y
Tom Rini2c7a8d42019-08-14 08:11:27 -0400[diff] [blame]10CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
Tom Rini2c7a8d42019-08-14 08:11:27 -0400[diff] [blame]11CONFIG_TPL_LIBCOMMON_SUPPORT=y
12CONFIG_TPL_LIBGENERIC_SUPPORT=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]13CONFIG_SPL_DRIVERS_MISC=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]14CONFIG_SPL_STACK_R_ADDR=0x600000
15CONFIG_DEBUG_UART_BASE=0xFF130000
16CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]17CONFIG_SYS_LOAD_ADDR=0x800800
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]18CONFIG_DEBUG_UART=y
Tom Rini2c7a8d42019-08-14 08:11:27 -0400[diff] [blame]19CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]20# CONFIG_ANDROID_BOOT_IMAGE is not set
21CONFIG_FIT=y
22CONFIG_FIT_VERBOSE=y
23CONFIG_SPL_LOAD_FIT=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]24CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb"
25# CONFIG_DISPLAY_CPUINFO is not set
26CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]27CONFIG_MISC_INIT_R=y
Kever Yang1b0675a2019-08-20 11:47:00 +0800[diff] [blame]28# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rini2c7a8d42019-08-14 08:11:27 -0400[diff] [blame]29CONFIG_TPL_SYS_MALLOC_SIMPLE=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]30CONFIG_SPL_STACK_R=y
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]31CONFIG_SPL_I2C=y
Simon Glasse91ac4c2021-07-10 21:14:24 -0600[diff] [blame]32CONFIG_SPL_POWER=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]33CONFIG_SPL_ATF=y
34CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]35CONFIG_CMD_BOOTZ=y
36CONFIG_CMD_GPT=y
37CONFIG_CMD_MMC=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]38CONFIG_CMD_USB=y
39# CONFIG_CMD_SETEXPR is not set
40CONFIG_CMD_TIME=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]41CONFIG_SPL_OF_CONTROL=y
Matwey V. Kornilov65785a22019-08-02 10:40:03 +0300[diff] [blame]42CONFIG_TPL_OF_CONTROL=y
Kurt Miller2e208462020-05-13 15:55:20 -0400[diff] [blame]43CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Matwey V. Kornilov65785a22019-08-02 10:40:03 +0300[diff] [blame]44CONFIG_TPL_OF_PLATDATA=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]45CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]46CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinieb1f9092020-07-24 17:14:47 -0400[diff] [blame]47CONFIG_SYS_MMC_ENV_DEV=1
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]48CONFIG_NET_RANDOM_ETHADDR=y
Tom Rini2c7a8d42019-08-14 08:11:27 -0400[diff] [blame]49CONFIG_TPL_DM=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]50CONFIG_REGMAP=y
51CONFIG_SPL_REGMAP=y
Matwey V. Kornilov65785a22019-08-02 10:40:03 +0300[diff] [blame]52CONFIG_TPL_REGMAP=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]53CONFIG_SYSCON=y
54CONFIG_SPL_SYSCON=y
Matwey V. Kornilov65785a22019-08-02 10:40:03 +0300[diff] [blame]55CONFIG_TPL_SYSCON=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]56CONFIG_CLK=y
57CONFIG_SPL_CLK=y
Tom Rini2c7a8d42019-08-14 08:11:27 -0400[diff] [blame]58CONFIG_FASTBOOT_BUF_ADDR=0x800800
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]59CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
60CONFIG_ROCKCHIP_GPIO=y
61CONFIG_SYS_I2C_ROCKCHIP=y
62CONFIG_MMC_DW=y
63CONFIG_MMC_DW_ROCKCHIP=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]64CONFIG_SF_DEFAULT_SPEED=20000000
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]65CONFIG_SPI_FLASH_GIGADEVICE=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]66CONFIG_DM_ETH=y
67CONFIG_ETH_DESIGNWARE=y
68CONFIG_GMAC_ROCKCHIP=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]69CONFIG_PINCTRL=y
70CONFIG_SPL_PINCTRL=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]71CONFIG_DM_PMIC=y
72CONFIG_PMIC_RK8XX=y
Simon Glass6343ffb2021-08-08 12:20:25 -0600[diff] [blame]73CONFIG_SPL_PMIC_RK8XX=y
Kurt Miller2e208462020-05-13 15:55:20 -0400[diff] [blame]74CONFIG_SPL_DM_REGULATOR=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]75CONFIG_REGULATOR_PWM=y
76CONFIG_DM_REGULATOR_FIXED=y
Tom Rini63683ef2020-05-26 08:32:25 -0400[diff] [blame]77CONFIG_SPL_DM_REGULATOR_FIXED=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]78CONFIG_REGULATOR_RK8XX=y
79CONFIG_PWM_ROCKCHIP=y
80CONFIG_RAM=y
81CONFIG_SPL_RAM=y
Matwey V. Kornilov65785a22019-08-02 10:40:03 +0300[diff] [blame]82CONFIG_TPL_RAM=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]83CONFIG_DM_RESET=y
84CONFIG_BAUDRATE=1500000
85CONFIG_DEBUG_UART_SHIFT=2
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]86CONFIG_ROCKCHIP_SPI=y
Tom Rini4c66e9a2020-11-09 14:23:01 -0500[diff] [blame]87CONFIG_SYSINFO=y
88CONFIG_SYSINFO_SMBIOS=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]89CONFIG_SYSRESET=y
YouMin Chenb9f7df32019-11-15 11:04:44 +0800[diff] [blame]90# CONFIG_TPL_SYSRESET is not set
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]91CONFIG_USB=y
92CONFIG_USB_XHCI_HCD=y
93CONFIG_USB_XHCI_DWC3=y
94CONFIG_USB_EHCI_HCD=y
95CONFIG_USB_EHCI_GENERIC=y
96CONFIG_USB_OHCI_HCD=y
97CONFIG_USB_OHCI_GENERIC=y
98CONFIG_USB_DWC2=y
99CONFIG_USB_DWC3=y
Jean-Jacques Hiblot731a2a32019-09-11 11:33:53 +0200[diff] [blame]100# CONFIG_USB_DWC3_GADGET is not set
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]101CONFIG_USB_GADGET=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]102CONFIG_USB_GADGET_DWC2_OTG=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]103CONFIG_SPL_TINY_MEMSET=y
Matwey V. Kornilov65785a22019-08-02 10:40:03 +0300[diff] [blame]104CONFIG_TPL_TINY_MEMSET=y
Matwey V. Kornilovc1d22df2019-06-09 00:27:17 +0300[diff] [blame]105CONFIG_ERRNO_STR=y