blob: 4c6d5bed447fdf0431145ef0a0e3892c75c1b271 [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +08001// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
4
5/ {
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&gic>;
9
10 /* external reference clock */
11 clk_refclk: clk-refclk {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <25000000>;
15 clock-output-names = "refclk";
16 };
17
18 ahb {
19 rstc: reset-controller@f0801000 {
20 compatible = "nuvoton,npcm845-reset", "syscon",
21 "simple-mfd";
22 reg = <0x0 0xf0801000 0x0 0xC4>;
23 rstc1: reset-controller1 {
24 compatible = "syscon-reset";
25 #reset-cells = <1>;
26 regmap = <&rstc>;
27 offset = <NPCM8XX_RESET_IPSRST1>;
28 mask = <0xFFFFFFFF>;
29 };
30 rstc2: reset-controller2 {
31 compatible = "syscon-reset";
32 #reset-cells = <1>;
33 regmap = <&rstc>;
34 offset = <NPCM8XX_RESET_IPSRST2>;
35 mask = <0xFFFFFFFF>;
36 };
37 rstc3: reset-controller3 {
38 compatible = "syscon-reset";
39 #reset-cells = <1>;
40 regmap = <&rstc>;
41 offset = <NPCM8XX_RESET_IPSRST3>;
42 mask = <0xFFFFFFFF>;
43 };
44 rstc4: reset-controller4 {
45 compatible = "syscon-reset";
46 #reset-cells = <1>;
47 regmap = <&rstc>;
48 offset = <NPCM8XX_RESET_IPSRST4>;
49 mask = <0xFFFFFFFF>;
50 };
51 };
52
53 clk: clock-controller@f0801000 {
54 compatible = "nuvoton,npcm845-clk", "syscon";
55 #clock-cells = <1>;
56 clock-controller;
57 reg = <0x0 0xf0801000 0x0 0x1000>;
58 clock-names = "refclk";
59 clocks = <&clk_refclk>;
60 };
61
Jim Liu2e4fb4e2023-01-17 16:59:21 +080062 gmac0: eth@f0802000 {
63 device_type = "network";
64 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
65 reg = <0x0 0xf0802000 0x0 0x2000>,
66 <0x0 0xf0780000 0x0 0x200>;
67 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
68 interrupt-names = "macirq";
69 clocks = <&clk NPCM8XX_CLK_AHB>;
70 clock-names = "stmmaceth";
71 pinctrl-names = "default";
72 pinctrl-0 = <&rg1mdio_pins>;
73 resets = <&rstc2 NPCM8XX_RESET_GMAC1>;
74 status = "disabled";
75 };
76
77 gmac1: eth@f0804000 {
78 device_type = "network";
79 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
80 reg = <0x0 0xf0804000 0x0 0x2000>;
81 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
82 interrupt-names = "macirq";
83 clocks = <&clk NPCM8XX_CLK_AHB>;
84 clock-names = "stmmaceth";
85 pinctrl-names = "default";
86 pinctrl-0 = <&rg2_pins
87 &rg2mdio_pins>;
88 resets = <&rstc2 NPCM8XX_RESET_GMAC2>;
89 status = "disabled";
90 };
91
92 gmac2: eth@f0806000 {
93 device_type = "network";
94 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
95 reg = <0x0 0xf0806000 0x0 0x2000>;
96 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-names = "macirq";
98 clocks = <&clk NPCM8XX_CLK_AHB>;
99 clock-names = "stmmaceth";
100 pinctrl-names = "default";
101 pinctrl-0 = <&r1_pins
102 &r1err_pins
103 &r1md_pins>;
104 resets = <&rstc1 NPCM8XX_RESET_GMAC3>;
105 status = "disabled";
106 };
107
108 gmac3: eth@f0808000 {
109 device_type = "network";
110 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
111 reg = <0x0 0xf0808000 0x0 0x2000>;
112 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
113 interrupt-names = "macirq";
114 clocks = <&clk NPCM8XX_CLK_AHB>;
115 clock-names = "stmmaceth";
116 pinctrl-names = "default";
117 pinctrl-0 = <&r2_pins
118 &r2err_pins
119 &r2md_pins>;
120 resets = <&rstc1 NPCM8XX_RESET_GMAC4>;
121 status = "disabled";
122 };
123
Jim Liu89b26542022-11-28 10:32:44 +0800124 ehci1: usb@f0828100 {
125 compatible = "nuvoton,npcm845-ehci";
126 reg = <0x0 0xf0828100 0x0 0x1000>;
127 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
128 resets = <&rstc2 NPCM8XX_RESET_USBH1>;
129 status = "disabled";
130 };
131
132 ehci2: usb@f082a100 {
133 compatible = "nuvoton,npcm845-ehci";
134 reg = <0x0 0xf082a100 0x0 0x1000>;
135 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
136 resets = <&rstc4 NPCM8XX_RESET_USBH2>;
137 status = "disabled";
138 };
139
140 ohci1: usb@f0829000 {
141 compatible = "nuvoton,npcm845-ohci";
142 reg = <0x0 0xF0829000 0x0 0x1000>;
143 resets = <&rstc2 NPCM8XX_RESET_USBH1>;
144 status = "disabled";
145 };
146
147 ohci2: usb@f082b000 {
148 compatible = "nuvoton,npcm845-ohci";
149 reg = <0x0 0xF082B000 0x0 0x1000>;
150 resets = <&rstc4 NPCM8XX_RESET_USBH2>;
151 status = "disabled";
152 };
153
154 usbphy {
155 compatible = "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <0>;
158 syscon = <&gcr>;
159 usbphy1: usbphy@1 {
160 compatible = "nuvoton,npcm845-usb-phy";
161 #phy-cells = <1>;
162 reg = <1>;
163 resets = <&rstc3 NPCM8XX_RESET_USBPHY1>;
164 status = "disabled";
165 };
166 usbphy2: usbphy@2 {
167 compatible = "nuvoton,npcm845-usb-phy";
168 #phy-cells = <1>;
169 reg = <2>;
170 resets = <&rstc3 NPCM8XX_RESET_USBPHY2>;
171 status = "disabled";
172 };
173 usbphy3: usbphy@3 {
174 compatible = "nuvoton,npcm845-usb-phy";
175 #phy-cells = <1>;
176 reg = <3>;
Jim Liu4ddc8d42023-11-14 16:51:56 +0800177 resets = <&rstc4 NPCM8XX_RESET_USBPHY3>;
Jim Liu89b26542022-11-28 10:32:44 +0800178 status = "disabled";
179 };
180 };
181
182 udc0:udc@f0830100 {
183 compatible = "nuvoton,npcm845-udc";
184 reg = <0x0 0xf0830100 0x0 0x100
185 0x0 0xfffb0000 0x0 0x800>;
186 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clk NPCM8XX_CLK_SU>;
188 clock-names = "clk_usb_bridge";
189 resets = <&rstc3 NPCM8XX_RESET_UDC0>;
190 status = "disable";
191 };
192
193 udc1:udc@f0831100 {
194 compatible = "nuvoton,npcm845-udc";
195 reg = <0x0 0xf0831100 0x0 0x100
196 0x0 0xfffb0800 0x0 0x800>;
197 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clk NPCM8XX_CLK_SU>;
199 clock-names = "clk_usb_bridge";
200 resets = <&rstc1 NPCM8XX_RESET_UDC1>;
201 status = "disable";
202 };
203
204 udc2:udc@f0832100 {
205 compatible = "nuvoton,npcm845-udc";
206 reg = <0x0 0xf0832100 0x0 0x100
207 0x0 0xfffb1000 0x0 0x800>;
208 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&clk NPCM8XX_CLK_SU>;
210 clock-names = "clk_usb_bridge";
211 resets = <&rstc1 NPCM8XX_RESET_UDC2>;
212 status = "disable";
213 };
214
215 udc3:udc@f0833100 {
216 compatible = "nuvoton,npcm845-udc";
217 reg = <0x0 0xf0833100 0x0 0x100
218 0x0 0xfffb1800 0x0 0x800>;
219 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&clk NPCM8XX_CLK_SU>;
221 clock-names = "clk_usb_bridge";
222 resets = <&rstc1 NPCM8XX_RESET_UDC3>;
223 status = "disable";
224 };
225
226 udc4:udc@f0834100 {
227 compatible = "nuvoton,npcm845-udc";
228 reg = <0x0 0xf0834100 0x0 0x100
229 0x0 0xfffb2000 0x0 0x800>;
230 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clk NPCM8XX_CLK_SU>;
232 clock-names = "clk_usb_bridge";
233 resets = <&rstc1 NPCM8XX_RESET_UDC4>;
234 status = "disable";
235 };
236
237 udc5:udc@f0835100 {
238 compatible = "nuvoton,npcm845-udc";
239 reg = <0x0 0xf0835100 0x0 0x100
240 0x0 0xfffb2800 0x0 0x800>;
241 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clk NPCM8XX_CLK_SU>;
243 clock-names = "clk_usb_bridge";
244 resets = <&rstc1 NPCM8XX_RESET_UDC5>;
245 status = "disable";
246 };
247
248 udc6:udc@f0836100 {
249 compatible = "nuvoton,npcm845-udc";
250 reg = <0x0 0xf0836100 0x0 0x100
251 0x0 0xfffb3000 0x0 0x800>;
252 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&clk NPCM8XX_CLK_SU>;
254 clock-names = "clk_usb_bridge";
255 resets = <&rstc1 NPCM8XX_RESET_UDC6>;
256 status = "disable";
257 };
258
259 udc7:udc@f0837100 {
260 compatible = "nuvoton,npcm845-udc";
261 reg = <0x0 0xf0837100 0x0 0x100
262 0x0 0xfffb3800 0x0 0x800>;
263 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clk NPCM8XX_CLK_SU>;
265 clock-names = "clk_usb_bridge";
266 resets = <&rstc3 NPCM8XX_RESET_UDC7>;
267 status = "disable";
268 };
269
270 udc8:udc@f0838100 {
271 compatible = "nuvoton,npcm845-udc";
272 reg = <0x0 0xf0838100 0x0 0x100
273 0x0 0xfffb4000 0x0 0x800>;
274 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&clk NPCM8XX_CLK_SU>;
276 clock-names = "clk_usb_bridge";
277 resets = <&rstc3 NPCM8XX_RESET_UDC8>;
278 status = "disable";
279 };
280
281 udc9:udc@f0839100 {
282 compatible = "nuvoton,npcm845-udc";
283 reg = <0x0 0xf0839100 0x0 0x100
284 0x0 0xfffb4800 0x0 0x800>;
285 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clk NPCM8XX_CLK_SU>;
287 clock-names = "clk_usb_bridge";
288 resets = <&rstc3 NPCM8XX_RESET_UDC9>;
289 status = "disable";
290 };
291
Jim Liu60bfc902023-06-13 15:45:55 +0800292 aes: aes@f0858000 {
293 compatible = "nuvoton,npcm845-aes";
294 reg = <0x0 0xf0858000 0x0 0x1000>,
295 <0x0 0xf0851000 0x0 0x1000>;
296 status = "disabled";
297 clocks = <&clk NPCM8XX_CLK_AHB>;
298 clock-names = "clk_ahb";
299 };
300
301 sha:sha@f085a000 {
302 compatible = "nuvoton,npcm845-sha";
303 reg = <0x0 0xf085a000 0x0 0x1000>;
304 status = "disabled";
305 clocks = <&clk NPCM8XX_CLK_AHB>;
306 clock-names = "clk_ahb";
307 };
308
Jim Liu147c0002022-09-27 16:45:15 +0800309 apb {
310 serial0: serial@0 {
311 compatible = "nuvoton,npcm845-uart";
312 reg = <0x0 0x1000>;
313 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
314 clock-frequency = <24000000>;
315 status = "disabled";
316 };
317
Jim Liu2e4fb4e2023-01-17 16:59:21 +0800318 serial1: serial@1000 {
319 compatible = "nuvoton,npcm845-uart";
320 reg = <0x1000 0x1000>;
321 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
322 status = "disabled";
323 };
324
325 serial2: serial@2000 {
326 compatible = "nuvoton,npcm845-uart";
327 reg = <0x2000 0x1000>;
328 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
329 status = "disabled";
330 };
331
332 serial3: serial@3000 {
333 compatible = "nuvoton,npcm845-uart";
334 reg = <0x3000 0x1000>;
335 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
336 status = "disabled";
337 };
338
339 serial4: serial@4000 {
340 compatible = "nuvoton,npcm845-uart";
341 reg = <0x4000 0x1000>;
342 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
343 status = "disabled";
344 };
345
346 serial5: serial@5000 {
347 compatible = "nuvoton,npcm845-uart";
348 reg = <0x5000 0x1000>;
349 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
350 status = "disabled";
351 };
352
353 serial6: serial@6000 {
354 compatible = "nuvoton,npcm845-uart";
355 reg = <0x6000 0x1000>;
356 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
357 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
358 status = "disabled";
359 };
360
Jim Liu147c0002022-09-27 16:45:15 +0800361 gpio0: gpio0@10000 {
Jim Liu89b26542022-11-28 10:32:44 +0800362 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800363 reg = <0x10000 0xB0>;
364 #gpio-cells = <2>;
365 gpio-controller;
366 gpio-bank-name = "gpio0";
367 };
368
369 gpio1: gpio1@11000 {
Jim Liu89b26542022-11-28 10:32:44 +0800370 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800371 reg = <0x11000 0xB0>;
372 #gpio-cells = <2>;
373 gpio-controller;
374 gpio-bank-name = "gpio1";
375 };
376
377 gpio2: gpio2@12000 {
Jim Liu89b26542022-11-28 10:32:44 +0800378 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800379 reg = <0x12000 0xB0>;
380 #gpio-cells = <2>;
381 gpio-controller;
382 gpio-bank-name = "gpio2";
383 };
384
385 gpio3: gpio3@13000 {
Jim Liu89b26542022-11-28 10:32:44 +0800386 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800387 reg = <0x13000 0xB0>;
388 #gpio-cells = <2>;
389 gpio-controller;
390 gpio-bank-name = "gpio3";
391 };
392
393 gpio4: gpio4@14000 {
Jim Liu89b26542022-11-28 10:32:44 +0800394 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800395 reg = <0x14000 0xB0>;
396 #gpio-cells = <2>;
397 gpio-controller;
398 gpio-bank-name = "gpio4";
399 };
400
401 gpio5: gpio5@15000 {
Jim Liu89b26542022-11-28 10:32:44 +0800402 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800403 reg = <0x15000 0xB0>;
404 #gpio-cells = <2>;
405 gpio-controller;
406 gpio-bank-name = "gpio5";
407 };
408
409 gpio6: gpio6@16000 {
Jim Liu89b26542022-11-28 10:32:44 +0800410 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800411 reg = <0x16000 0xB0>;
412 #gpio-cells = <2>;
413 gpio-controller;
414 gpio-bank-name = "gpio6";
415 };
416
417 gpio7: gpio7@17000 {
Jim Liu89b26542022-11-28 10:32:44 +0800418 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
Jim Liu147c0002022-09-27 16:45:15 +0800419 reg = <0x17000 0xB0>;
420 #gpio-cells = <2>;
421 gpio-controller;
422 gpio-bank-name = "gpio7";
423 };
Jim Liu2e4fb4e2023-01-17 16:59:21 +0800424
425 rng: rng@b000 {
426 compatible = "nuvoton,npcm845-rng";
427 reg = <0xb000 0x8>;
428 status = "disabled";
429 };
430
431 otp: otp@189000 {
432 compatible = "nuvoton,npcm845-otp";
433 reg = <0x189000 0x1000>;
434 status = "disabled";
435 };
436
Jim Liu147c0002022-09-27 16:45:15 +0800437 };
438 };
Jim Liu89b26542022-11-28 10:32:44 +0800439 pinctrl: pinctrl@f0800000 {
440 compatible = "nuvoton,npcm845-pinctrl", "syscon", "simple-mfd";
441 reg = <0x0 0xf0010000 0x0 0x8000>;
442 syscon-gcr = <&gcr>;
443 syscon-rst = <&rstc>;
444 status = "okay";
445
446 iox1_pins: iox1-pins {
447 groups = "iox1";
448 function = "iox1";
449 };
450 iox2_pins: iox2-pins {
451 groups = "iox2";
452 function = "iox2";
453 };
454 smb1d_pins: smb1d-pins {
455 groups = "smb1d";
456 function = "smb1d";
457 };
458 smb2d_pins: smb2d-pins {
459 groups = "smb2d";
460 function = "smb2d";
461 };
462 lkgpo1_pins: lkgpo1-pins {
463 groups = "lkgpo1";
464 function = "lkgpo1";
465 };
466 lkgpo2_pins: lkgpo2-pins {
467 groups = "lkgpo2";
468 function = "lkgpo2";
469 };
470 ioxh_pins: ioxh-pins {
471 groups = "ioxh";
472 function = "ioxh";
473 };
474 gspi_pins: gspi-pins {
475 groups = "gspi";
476 function = "gspi";
477 };
478 smb5b_pins: smb5b-pins {
479 groups = "smb5b";
480 function = "smb5b";
481 };
482 smb5c_pins: smb5c-pins {
483 groups = "smb5c";
484 function = "smb5c";
485 };
486 lkgpo0_pins: lkgpo0-pins {
487 groups = "lkgpo0";
488 function = "lkgpo0";
489 };
490 pspi_pins: pspi-pins {
491 groups = "pspi";
492 function = "pspi";
493 };
494 vgadig_pins: vgadig-pins {
495 groups = "vgadig";
496 function = "vgadig";
497 };
498 jm1_pins: jm1-pins {
499 groups = "jm1";
500 function = "jm1";
501 };
502 jm2_pins: jm2-pins {
503 groups = "jm2";
504 function = "jm2";
505 };
506 smb4b_pins: smb4b-pins {
507 groups = "smb4b";
508 function = "smb4b";
509 };
510 smb4c_pins: smb4c-pins {
511 groups = "smb4c";
512 function = "smb4c";
513 };
514 smb15_pins: smb15-pins {
515 groups = "smb15";
516 function = "smb15";
517 };
518 smb16_pins: smb16-pins {
519 groups = "smb16";
520 function = "smb16";
521 };
522 smb17_pins: smb17-pins {
523 groups = "smb17";
524 function = "smb17";
525 };
526 smb18_pins: smb18-pins {
527 groups = "smb18";
528 function = "smb18";
529 };
530 smb19_pins: smb19-pins {
531 groups = "smb19";
532 function = "smb19";
533 };
534 smb20_pins: smb20-pins {
535 groups = "smb20";
536 function = "smb20";
537 };
538 smb21_pins: smb21-pins {
539 groups = "smb21";
540 function = "smb21";
541 };
542 smb22_pins: smb22-pins {
543 groups = "smb22";
544 function = "smb22";
545 };
546 smb23_pins: smb23-pins {
547 groups = "smb23";
548 function = "smb23";
549 };
550 smb4d_pins: smb4d-pins {
551 groups = "smb4d";
552 function = "smb4d";
553 };
554 smb14_pins: smb14-pins {
555 groups = "smb14";
556 function = "smb14";
557 };
558 smb5_pins: smb5-pins {
559 groups = "smb5";
560 function = "smb5";
561 };
562 smb4_pins: smb4-pins {
563 groups = "smb4";
564 function = "smb4";
565 };
566 smb3_pins: smb3-pins {
567 groups = "smb3";
568 function = "smb3";
569 };
570 spi0cs1_pins: spi0cs1-pins {
571 groups = "spi0cs1";
572 function = "spi0cs1";
573 };
574 spi0cs2_pins: spi0cs2-pins {
575 groups = "spi0cs2";
576 function = "spi0cs2";
577 };
578 spi0cs3_pins: spi0cs3-pins {
579 groups = "spi0cs3";
580 function = "spi0cs3";
581 };
582 smb3c_pins: smb3c-pins {
583 groups = "smb3c";
584 function = "smb3c";
585 };
586 smb3b_pins: smb3b-pins {
587 groups = "smb3b";
588 function = "smb3b";
589 };
590 hsi1a_pins: hsi1a-pins {
591 groups = "hsi1a";
592 function = "hsi1a";
593 };
594 hsi1b_pins: hsi1b-pins {
595 groups = "hsi1b";
596 function = "hsi1b";
597 };
598 hsi1c_pins: hsi1c-pins {
599 groups = "hsi1c";
600 function = "hsi1c";
601 };
602 hsi2a_pins: hsi2a-pins {
603 groups = "hsi2a";
604 function = "hsi2a";
605 };
606 hsi2b_pins: hsi2b-pins {
607 groups = "hsi2b";
608 function = "hsi2b";
609 };
610 hsi2c_pins: hsi2c-pins {
611 groups = "hsi2c";
612 function = "hsi2c";
613 };
614 bmcuart0a_pins: bmcuart0a-pins {
615 groups = "bmcuart0a";
616 function = "bmcuart0a";
617 };
618 bmcuart0b_pins: bmcuart0b-pins {
619 groups = "bmcuart0b";
620 function = "bmcuart0b";
621 };
622 bmcuart1_pins: bmcuart1-pins {
623 groups = "bmcuart1";
624 function = "bmcuart1";
625 };
626 bu4_pins: bu4-pins {
627 groups = "bu4";
628 function = "bu4";
629 };
630 bu5_pins: bu5-pins {
631 groups = "bu5";
632 function = "bu5";
633 };
634 bu6_pins: bu6-pins {
635 groups = "bu6";
636 function = "bu6";
637 };
638 r1err_pins: r1err-pins {
639 groups = "r1err";
640 function = "r1err";
641 };
642 r1md_pins: r1md-pins {
643 groups = "r1md";
644 function = "r1md";
645 };
646 r1oen_pins: r1oen-pins {
647 groups = "r1oen";
648 function = "r1oen";
649 };
650 r1en_pins: r1en-pins {
651 groups = "r1en";
652 function = "r1en";
653 };
654 r2oen_pins: r2oen-pins {
655 groups = "r2oen";
656 function = "r2oen";
657 };
658 r2en_pins: r2en-pins {
659 groups = "r2en";
660 function = "r2en";
661 };
662 rmii3_pins: rmii3_pins {
663 groups = "rmii3";
664 function = "rmii3";
665 };
666 r3oen_pins: r3oen-pins {
667 groups = "r3oen";
668 function = "r3oen";
669 };
670 r3en_pins: r3en-pins {
671 groups = "r3en";
672 function = "r3en";
673 };
674 smb3d_pins: smb3d-pins {
675 groups = "smb3d";
676 function = "smb3d";
677 };
678 fanin0_pins: fanin0-pins {
679 groups = "fanin0";
680 function = "fanin0";
681 };
682 fanin1_pins: fanin1-pins {
683 groups = "fanin1";
684 function = "fanin1";
685 };
686 fanin2_pins: fanin2-pins {
687 groups = "fanin2";
688 function = "fanin2";
689 };
690 fanin3_pins: fanin3-pins {
691 groups = "fanin3";
692 function = "fanin3";
693 };
694 fanin4_pins: fanin4-pins {
695 groups = "fanin4";
696 function = "fanin4";
697 };
698 fanin5_pins: fanin5-pins {
699 groups = "fanin5";
700 function = "fanin5";
701 };
702 fanin6_pins: fanin6-pins {
703 groups = "fanin6";
704 function = "fanin6";
705 };
706 fanin7_pins: fanin7-pins {
707 groups = "fanin7";
708 function = "fanin7";
709 };
710 fanin8_pins: fanin8-pins {
711 groups = "fanin8";
712 function = "fanin8";
713 };
714 fanin9_pins: fanin9-pins {
715 groups = "fanin9";
716 function = "fanin9";
717 };
718 fanin10_pins: fanin10-pins {
719 groups = "fanin10";
720 function = "fanin10";
721 };
722 fanin11_pins: fanin11-pins {
723 groups = "fanin11";
724 function = "fanin11";
725 };
726 fanin12_pins: fanin12-pins {
727 groups = "fanin12";
728 function = "fanin12";
729 };
730 fanin13_pins: fanin13-pins {
731 groups = "fanin13";
732 function = "fanin13";
733 };
734 fanin14_pins: fanin14-pins {
735 groups = "fanin14";
736 function = "fanin14";
737 };
738 fanin15_pins: fanin15-pins {
739 groups = "fanin15";
740 function = "fanin15";
741 };
742 pwm0_pins: pwm0-pins {
743 groups = "pwm0";
744 function = "pwm0";
745 };
746 pwm1_pins: pwm1-pins {
747 groups = "pwm1";
748 function = "pwm1";
749 };
750 pwm2_pins: pwm2-pins {
751 groups = "pwm2";
752 function = "pwm2";
753 };
754 pwm3_pins: pwm3-pins {
755 groups = "pwm3";
756 function = "pwm3";
757 };
758 r2_pins: r2-pins {
759 groups = "r2";
760 function = "r2";
761 };
762 r2err_pins: r2err-pins {
763 groups = "r2err";
764 function = "r2err";
765 };
766 r2md_pins: r2md-pins {
767 groups = "r2md";
768 function = "r2md";
769 };
770 r3rxer_pins: r3rxer_pins {
771 groups = "r3rxer";
772 function = "r3rxer";
773 };
774 ga20kbc_pins: ga20kbc-pins {
775 groups = "ga20kbc";
776 function = "ga20kbc";
777 };
778 smb5d_pins: smb5d-pins {
779 groups = "smb5d";
780 function = "smb5d";
781 };
782 lpc_pins: lpc-pins {
783 groups = "lpc";
784 function = "lpc";
785 };
786 espi_pins: espi-pins {
787 groups = "espi";
788 function = "espi";
789 };
790 rg1_pins: rg1-pins {
791 groups = "rg1";
792 function = "rg1";
793 };
794 rg1mdio_pins: rg1mdio-pins {
795 groups = "rg1mdio";
796 function = "rg1mdio";
797 };
798 rg2_pins: rg2-pins {
799 groups = "rg2";
800 function = "rg2";
801 };
802 ddr_pins: ddr-pins {
803 groups = "ddr";
804 function = "ddr";
805 };
806 i3c0_pins: i3c0-pins {
807 groups = "i3c0";
808 function = "i3c0";
809 };
810 i3c1_pins: i3c1-pins {
811 groups = "i3c1";
812 function = "i3c1";
813 };
814 i3c2_pins: i3c2-pins {
815 groups = "i3c2";
816 function = "i3c2";
817 };
818 i3c3_pins: i3c3-pins {
819 groups = "i3c3";
820 function = "i3c3";
821 };
822 i3c4_pins: i3c4-pins {
823 groups = "i3c4";
824 function = "i3c4";
825 };
826 i3c5_pins: i3c5-pins {
827 groups = "i3c5";
828 function = "i3c5";
829 };
830 smb0_pins: smb0-pins {
831 groups = "smb0";
832 function = "smb0";
833 };
834 smb1_pins: smb1-pins {
835 groups = "smb1";
836 function = "smb1";
837 };
838 smb2_pins: smb2-pins {
839 groups = "smb2";
840 function = "smb2";
841 };
842 smb2c_pins: smb2c-pins {
843 groups = "smb2c";
844 function = "smb2c";
845 };
846 smb2b_pins: smb2b-pins {
847 groups = "smb2b";
848 function = "smb2b";
849 };
850 smb1c_pins: smb1c-pins {
851 groups = "smb1c";
852 function = "smb1c";
853 };
854 smb1b_pins: smb1b-pins {
855 groups = "smb1b";
856 function = "smb1b";
857 };
858 smb8_pins: smb8-pins {
859 groups = "smb8";
860 function = "smb8";
861 };
862 smb9_pins: smb9-pins {
863 groups = "smb9";
864 function = "smb9";
865 };
866 smb10_pins: smb10-pins {
867 groups = "smb10";
868 function = "smb10";
869 };
870 smb11_pins: smb11-pins {
871 groups = "smb11";
872 function = "smb11";
873 };
874 sd1_pins: sd1-pins {
875 groups = "sd1";
876 function = "sd1";
877 };
878 sd1pwr_pins: sd1pwr-pins {
879 groups = "sd1pwr";
880 function = "sd1pwr";
881 };
882 pwm4_pins: pwm4-pins {
883 groups = "pwm4";
884 function = "pwm4";
885 };
886 pwm5_pins: pwm5-pins {
887 groups = "pwm5";
888 function = "pwm5";
889 };
890 pwm6_pins: pwm6-pins {
891 groups = "pwm6";
892 function = "pwm6";
893 };
894 pwm7_pins: pwm7-pins {
895 groups = "pwm7";
896 function = "pwm7";
897 };
898 pwm8_pins: pwm8-pins {
899 groups = "pwm8";
900 function = "pwm8";
901 };
902 pwm9_pins: pwm9-pins {
903 groups = "pwm9";
904 function = "pwm9";
905 };
906 pwm10_pins: pwm10-pins {
907 groups = "pwm10";
908 function = "pwm10";
909 };
910 pwm11_pins: pwm11-pins {
911 groups = "pwm11";
912 function = "pwm11";
913 };
914 mmc8_pins: mmc8-pins {
915 groups = "mmc8";
916 function = "mmc8";
917 };
918 mmc_pins: mmc-pins {
919 groups = "mmc";
920 function = "mmc";
921 };
922 mmcwp_pins: mmcwp-pins {
923 groups = "mmcwp";
924 function = "mmcwp";
925 };
926 mmccd_pins: mmccd-pins {
927 groups = "mmccd";
928 function = "mmccd";
929 };
930 mmcrst_pins: mmcrst-pins {
931 groups = "mmcrst";
932 function = "mmcrst";
933 };
934 clkout_pins: clkout-pins {
935 groups = "clkout";
936 function = "clkout";
937 };
938 serirq_pins: serirq-pins {
939 groups = "serirq";
940 function = "serirq";
941 };
942 scipme_pins: scipme-pins {
943 groups = "scipme";
944 function = "scipme";
945 };
946 sci_pins: sci-pins {
947 groups = "sci";
948 function = "sci";
949 };
950 smb6_pins: smb6-pins {
951 groups = "smb6";
952 function = "smb6";
953 };
954 smb7_pins: smb7-pins {
955 groups = "smb7";
956 function = "smb7";
957 };
958 spi1_pins: spi1-pins {
959 groups = "spi1";
960 function = "spi1";
961 };
962 spi1d23_pins: spi1d23-pins {
963 groups = "spi1d23";
964 function = "spi1d23";
965 };
966 faninx_pins: faninx-pins {
967 groups = "faninx";
968 function = "faninx";
969 };
970 r1_pins: r1-pins {
971 groups = "r1";
972 function = "r1";
973 };
974 spi3_pins: spi3-pins {
975 groups = "spi3";
976 function = "spi3";
977 };
978 spi3cs1_pins: spi3cs1-pins {
979 groups = "spi3cs1";
980 function = "spi3cs1";
981 };
982 spi3quad_pins: spi3quad-pins {
983 groups = "spi3quad";
984 function = "spi3quad";
985 };
986 spi3cs2_pins: spi3cs2-pins {
987 groups = "spi3cs2";
988 function = "spi3cs2";
989 };
990 spi3cs3_pins: spi3cs3-pins {
991 groups = "spi3cs3";
992 function = "spi3cs3";
993 };
994 nprd_smi_pins: nprd-smi-pins {
995 groups = "nprd_smi";
996 function = "nprd_smi";
997 };
998 smb0b_pins: smb0b-pins {
999 groups = "smb0b";
1000 function = "smb0b";
1001 };
1002 smb0c_pins: smb0c-pins {
1003 groups = "smb0c";
1004 function = "smb0c";
1005 };
1006 smb0den_pins: smb0den-pins {
1007 groups = "smb0den";
1008 function = "smb0den";
1009 };
1010 smb0d_pins: smb0d-pins {
1011 groups = "smb0d";
1012 function = "smb0d";
1013 };
1014 rg2mdio_pins: rg2mdio-pins {
1015 groups = "rg2mdio";
1016 function = "rg2mdio";
1017 };
1018 rg2refck_pins: rg2refck-pins {
1019 groups = "rg2refck";
1020 function = "rg2refck";
1021 };
1022 wdog1_pins: wdog1-pins {
1023 groups = "wdog1";
1024 function = "wdog1";
1025 };
1026 wdog2_pins: wdog2-pins {
1027 groups = "wdog2";
1028 function = "wdog2";
1029 };
1030 smb12_pins: smb12-pins {
1031 groups = "smb12";
1032 function = "smb12";
1033 };
1034 smb13_pins: smb13-pins {
1035 groups = "smb13";
1036 function = "smb13";
1037 };
1038 spix_pins: spix-pins {
1039 groups = "spix";
1040 function = "spix";
1041 };
1042 spixcs1_pins: spixcs1-pins {
1043 groups = "spixcs1";
1044 function = "spixcs1";
1045 };
1046 clkreq_pins: clkreq-pins {
1047 groups = "clkreq";
1048 function = "clkreq";
1049 };
1050 hgpio0_pins: hgpio0-pins {
1051 groups = "hgpio0";
1052 function = "hgpio0";
1053 };
1054 hgpio1_pins: hgpio1-pins {
1055 groups = "hgpio1";
1056 function = "hgpio1";
1057 };
1058 hgpio2_pins: hgpio2-pins {
1059 groups = "hgpio2";
1060 function = "hgpio2";
1061 };
1062 hgpio3_pins: hgpio3-pins {
1063 groups = "hgpio3";
1064 function = "hgpio3";
1065 };
1066 hgpio4_pins: hgpio4-pins {
1067 groups = "hgpio4";
1068 function = "hgpio4";
1069 };
1070 hgpio5_pins: hgpio5-pins {
1071 groups = "hgpio5";
1072 function = "hgpio5";
1073 };
1074 hgpio6_pins: hgpio6-pins {
1075 groups = "hgpio6";
1076 function = "hgpio6";
1077 };
1078 hgpio7_pins: hgpio7-pins {
1079 groups = "hgpio7";
1080 function = "hgpio7";
1081 };
1082 jtag2_pins: jtag2-pins {
1083 groups = "jtag2";
1084 function = "jtag2";
1085 };
1086 };
Jim Liu147c0002022-09-27 16:45:15 +08001087};