Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2006 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 3bbe70c | 2019-12-28 10:44:54 -0700 | [diff] [blame] | 8 | #include <fdt_support.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 9 | #include <init.h> |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 10 | #include <ioports.h> |
| 11 | #include <mpc83xx.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame^] | 12 | #include <asm/bitops.h> |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 13 | #include <asm/mpc8349_pci.h> |
| 14 | #include <i2c.h> |
Ben Warren | 81362c1 | 2008-01-16 22:37:42 -0500 | [diff] [blame] | 15 | #include <spi.h> |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 16 | #include <miiphy.h> |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 17 | #ifdef CONFIG_SYS_FSL_DDR2 |
| 18 | #include <fsl_ddr_sdram.h> |
York Sun | c3c301e | 2011-08-26 11:32:45 -0700 | [diff] [blame] | 19 | #else |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 20 | #include <spd_sdram.h> |
York Sun | c3c301e | 2011-08-26 11:32:45 -0700 | [diff] [blame] | 21 | #endif |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 22 | #include <linux/delay.h> |
Jon Loeliger | de9737d | 2008-03-04 10:03:03 -0600 | [diff] [blame] | 23 | |
Kim Phillips | 3204c7c | 2007-12-20 15:57:28 -0600 | [diff] [blame] | 24 | #if defined(CONFIG_OF_LIBFDT) |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 25 | #include <linux/libfdt.h> |
Kim Phillips | 774e1b5 | 2006-11-01 00:10:40 -0600 | [diff] [blame] | 26 | #endif |
| 27 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 28 | DECLARE_GLOBAL_DATA_PTR; |
| 29 | |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 30 | int fixed_sdram(void); |
| 31 | void sdram_init(void); |
| 32 | |
Peter Tyser | 62e7398 | 2009-05-22 17:23:24 -0500 | [diff] [blame] | 33 | #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 34 | void ddr_enable_ecc(unsigned int dram_size); |
| 35 | #endif |
| 36 | |
| 37 | int board_early_init_f (void) |
| 38 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 39 | volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 40 | |
| 41 | /* Enable flash write */ |
| 42 | bcsr[1] &= ~0x01; |
| 43 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 44 | #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY |
Kumar Gala | 4c7efd8 | 2006-04-20 13:45:32 -0500 | [diff] [blame] | 45 | /* Use USB PHY on SYS board */ |
| 46 | bcsr[5] |= 0x02; |
| 47 | #endif |
| 48 | |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 49 | return 0; |
| 50 | } |
| 51 | |
| 52 | #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) |
| 53 | |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 54 | int dram_init(void) |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 55 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 56 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
York Sun | c3c301e | 2011-08-26 11:32:45 -0700 | [diff] [blame] | 57 | phys_size_t msize = 0; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 58 | |
| 59 | if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 60 | return -ENXIO; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 61 | |
| 62 | /* DDR SDRAM - Main SODIMM */ |
Mario Six | c9f9277 | 2019-01-21 09:18:15 +0100 | [diff] [blame] | 63 | im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 64 | #if defined(CONFIG_SPD_EEPROM) |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 65 | #ifndef CONFIG_SYS_FSL_DDR2 |
York Sun | c3c301e | 2011-08-26 11:32:45 -0700 | [diff] [blame] | 66 | msize = spd_sdram() * 1024 * 1024; |
| 67 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 68 | ddr_enable_ecc(msize); |
| 69 | #endif |
| 70 | #else |
| 71 | msize = fsl_ddr_sdram(); |
| 72 | #endif |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 73 | #else |
York Sun | c3c301e | 2011-08-26 11:32:45 -0700 | [diff] [blame] | 74 | msize = fixed_sdram() * 1024 * 1024; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 75 | #endif |
| 76 | /* |
| 77 | * Initialize SDRAM if it is on local bus. |
| 78 | */ |
| 79 | sdram_init(); |
| 80 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 81 | /* set total bus SDRAM size(bytes) -- DDR */ |
| 82 | gd->ram_size = msize; |
| 83 | |
| 84 | return 0; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | #if !defined(CONFIG_SPD_EEPROM) |
| 88 | /************************************************************************* |
| 89 | * fixed sdram init -- doesn't use serial presence detect. |
| 90 | ************************************************************************/ |
| 91 | int fixed_sdram(void) |
| 92 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 93 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
Joe Hershberger | 5ade390 | 2011-10-11 23:57:31 -0500 | [diff] [blame] | 94 | u32 msize = CONFIG_SYS_DDR_SIZE; |
| 95 | u32 ddr_size = msize << 20; /* DDR size in bytes */ |
| 96 | u32 ddr_size_log2 = __ilog2(ddr_size); |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 97 | |
Mario Six | 805cac1 | 2019-01-21 09:18:16 +0100 | [diff] [blame] | 98 | im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 99 | im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
Rafal Jaworowski | 4a9b6aa | 2006-03-16 17:46:46 +0100 | [diff] [blame] | 100 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 101 | #if (CONFIG_SYS_DDR_SIZE != 256) |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 102 | #warning Currenly any ddr size other than 256 is not supported |
| 103 | #endif |
Xie Xiaobo | 6149a5a | 2007-02-14 18:27:17 +0800 | [diff] [blame] | 104 | #ifdef CONFIG_DDR_II |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 105 | im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS; |
| 106 | im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; |
| 107 | im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
| 108 | im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 109 | im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
| 110 | im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
| 111 | im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; |
| 112 | im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; |
| 113 | im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; |
| 114 | im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; |
| 115 | im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
| 116 | im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; |
Xie Xiaobo | 6149a5a | 2007-02-14 18:27:17 +0800 | [diff] [blame] | 117 | #else |
Joe Hershberger | 5ade390 | 2011-10-11 23:57:31 -0500 | [diff] [blame] | 118 | |
Mario Six | 805cac1 | 2019-01-21 09:18:16 +0100 | [diff] [blame] | 119 | #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) |
Joe Hershberger | 5ade390 | 2011-10-11 23:57:31 -0500 | [diff] [blame] | 120 | #warning Chip select bounds is only configurable in 16MB increments |
| 121 | #endif |
| 122 | im->ddr.csbnds[2].csbnds = |
Mario Six | 805cac1 | 2019-01-21 09:18:16 +0100 | [diff] [blame] | 123 | ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | |
| 124 | (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> |
Joe Hershberger | 5ade390 | 2011-10-11 23:57:31 -0500 | [diff] [blame] | 125 | CSBNDS_EA_SHIFT) & CSBNDS_EA); |
| 126 | im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; |
Rafal Jaworowski | 4a9b6aa | 2006-03-16 17:46:46 +0100 | [diff] [blame] | 127 | |
Wolfgang Denk | ebd3deb | 2006-04-16 10:51:58 +0200 | [diff] [blame] | 128 | /* currently we use only one CS, so disable the other banks */ |
Rafal Jaworowski | 4a9b6aa | 2006-03-16 17:46:46 +0100 | [diff] [blame] | 129 | im->ddr.cs_config[0] = 0; |
| 130 | im->ddr.cs_config[1] = 0; |
| 131 | im->ddr.cs_config[3] = 0; |
| 132 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 134 | im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
Wolfgang Denk | ebd3deb | 2006-04-16 10:51:58 +0200 | [diff] [blame] | 135 | |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 136 | im->ddr.sdram_cfg = |
| 137 | SDRAM_CFG_SREN |
| 138 | #if defined(CONFIG_DDR_2T_TIMING) |
| 139 | | SDRAM_CFG_2T_EN |
| 140 | #endif |
| 141 | | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; |
Rafal Jaworowski | 4a9b6aa | 2006-03-16 17:46:46 +0100 | [diff] [blame] | 142 | #if defined (CONFIG_DDR_32BIT) |
| 143 | /* for 32-bit mode burst length is 8 */ |
| 144 | im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); |
| 145 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 146 | im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 147 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 148 | im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
Xie Xiaobo | 6149a5a | 2007-02-14 18:27:17 +0800 | [diff] [blame] | 149 | #endif |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 150 | udelay(200); |
| 151 | |
Rafal Jaworowski | 4a9b6aa | 2006-03-16 17:46:46 +0100 | [diff] [blame] | 152 | /* enable DDR controller */ |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 153 | im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 154 | return msize; |
| 155 | } |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | #endif/*!CONFIG_SYS_SPD_EEPROM*/ |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 157 | |
| 158 | |
| 159 | int checkboard (void) |
| 160 | { |
Ira W. Snyder | 4adfd02 | 2008-08-22 11:00:15 -0700 | [diff] [blame] | 161 | /* |
| 162 | * Warning: do not read the BCSR registers here |
| 163 | * |
| 164 | * There is a timing bug in the 8349E and 8349EA BCSR code |
| 165 | * version 1.2 (read from BCSR 11) that will cause the CFI |
| 166 | * flash initialization code to overwrite BCSR 0, disabling |
| 167 | * the serial ports and gigabit ethernet |
| 168 | */ |
| 169 | |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 170 | puts("Board: Freescale MPC8349EMDS\n"); |
| 171 | return 0; |
| 172 | } |
| 173 | |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 174 | /* |
| 175 | * if MPC8349EMDS is soldered with SDRAM |
| 176 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 177 | #if defined(CONFIG_SYS_BR2_PRELIM) \ |
| 178 | && defined(CONFIG_SYS_OR2_PRELIM) \ |
| 179 | && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ |
| 180 | && defined(CONFIG_SYS_LBLAWAR2_PRELIM) |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 181 | /* |
| 182 | * Initialize SDRAM memory on the Local Bus. |
| 183 | */ |
| 184 | |
| 185 | void sdram_init(void) |
| 186 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 188 | volatile fsl_lbc_t *lbc = &immap->im_lbc; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; |
Mario Six | dc00300 | 2019-01-21 09:18:17 +0100 | [diff] [blame] | 190 | const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | |
| 191 | LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | |
| 192 | LSDMR_WRC3 | LSDMR_CL3; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 193 | /* |
| 194 | * Setup SDRAM Base and Option Registers, already done in cpu_init.c |
| 195 | */ |
| 196 | |
| 197 | /* setup mtrpt, lsrt and lbcr for LB bus */ |
Mario Six | dc00300 | 2019-01-21 09:18:17 +0100 | [diff] [blame] | 198 | lbc->lbcr = 0x00000000; |
| 199 | /* LB refresh timer prescal, 266MHz/32 */ |
| 200 | lbc->mrtpr = 0x20000000; |
| 201 | /* LB sdram refresh timer, about 6us */ |
| 202 | lbc->lsrt = 0x32000000; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 203 | asm("sync"); |
| 204 | |
| 205 | /* |
| 206 | * Configure the SDRAM controller Machine Mode Register. |
| 207 | */ |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 208 | |
Mario Six | dc00300 | 2019-01-21 09:18:17 +0100 | [diff] [blame] | 209 | /* 0x40636733; normal operation */ |
| 210 | lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; |
| 211 | |
| 212 | /* 0x68636733; precharge all the banks */ |
| 213 | lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 214 | asm("sync"); |
| 215 | *sdram_addr = 0xff; |
| 216 | udelay(100); |
| 217 | |
Mario Six | dc00300 | 2019-01-21 09:18:17 +0100 | [diff] [blame] | 218 | /* 0x48636733; auto refresh */ |
| 219 | lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 220 | asm("sync"); |
| 221 | /*1 times*/ |
| 222 | *sdram_addr = 0xff; |
| 223 | udelay(100); |
| 224 | /*2 times*/ |
| 225 | *sdram_addr = 0xff; |
| 226 | udelay(100); |
| 227 | /*3 times*/ |
| 228 | *sdram_addr = 0xff; |
| 229 | udelay(100); |
| 230 | /*4 times*/ |
| 231 | *sdram_addr = 0xff; |
| 232 | udelay(100); |
| 233 | /*5 times*/ |
| 234 | *sdram_addr = 0xff; |
| 235 | udelay(100); |
| 236 | /*6 times*/ |
| 237 | *sdram_addr = 0xff; |
| 238 | udelay(100); |
| 239 | /*7 times*/ |
| 240 | *sdram_addr = 0xff; |
| 241 | udelay(100); |
| 242 | /*8 times*/ |
| 243 | *sdram_addr = 0xff; |
| 244 | udelay(100); |
| 245 | |
| 246 | /* 0x58636733; mode register write operation */ |
Mario Six | dc00300 | 2019-01-21 09:18:17 +0100 | [diff] [blame] | 247 | lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 248 | asm("sync"); |
| 249 | *sdram_addr = 0xff; |
| 250 | udelay(100); |
| 251 | |
Mario Six | dc00300 | 2019-01-21 09:18:17 +0100 | [diff] [blame] | 252 | /* 0x40636733; normal operation */ |
| 253 | lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 254 | asm("sync"); |
| 255 | *sdram_addr = 0xff; |
| 256 | udelay(100); |
| 257 | } |
| 258 | #else |
| 259 | void sdram_init(void) |
| 260 | { |
Marian Balakowicz | d7a3f72 | 2006-03-14 16:24:38 +0100 | [diff] [blame] | 261 | } |
| 262 | #endif |
Marian Balakowicz | 52ee4bd | 2006-03-16 15:19:35 +0100 | [diff] [blame] | 263 | |
Ben Warren | 81362c1 | 2008-01-16 22:37:42 -0500 | [diff] [blame] | 264 | /* |
| 265 | * The following are used to control the SPI chip selects for the SPI command. |
| 266 | */ |
Ben Warren | 20582da | 2008-06-08 23:28:33 -0700 | [diff] [blame] | 267 | #ifdef CONFIG_MPC8XXX_SPI |
Ben Warren | 81362c1 | 2008-01-16 22:37:42 -0500 | [diff] [blame] | 268 | |
| 269 | #define SPI_CS_MASK 0x80000000 |
| 270 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 271 | int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
| 272 | { |
| 273 | return bus == 0 && cs == 0; |
| 274 | } |
| 275 | |
| 276 | void spi_cs_activate(struct spi_slave *slave) |
Ben Warren | 81362c1 | 2008-01-16 22:37:42 -0500 | [diff] [blame] | 277 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 278 | volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; |
Ben Warren | 81362c1 | 2008-01-16 22:37:42 -0500 | [diff] [blame] | 279 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 280 | iopd->dat &= ~SPI_CS_MASK; |
Ben Warren | 81362c1 | 2008-01-16 22:37:42 -0500 | [diff] [blame] | 281 | } |
| 282 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 283 | void spi_cs_deactivate(struct spi_slave *slave) |
| 284 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 285 | volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; |
Ben Warren | 81362c1 | 2008-01-16 22:37:42 -0500 | [diff] [blame] | 286 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 287 | iopd->dat |= SPI_CS_MASK; |
| 288 | } |
Jagan Teki | 5931fbb | 2018-11-24 14:31:12 +0530 | [diff] [blame] | 289 | #endif |
Ben Warren | 81362c1 | 2008-01-16 22:37:42 -0500 | [diff] [blame] | 290 | |
Kim Phillips | 2141681 | 2007-08-15 22:30:33 -0500 | [diff] [blame] | 291 | #if defined(CONFIG_OF_BOARD_SETUP) |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 292 | int ft_board_setup(void *blob, bd_t *bd) |
Kim Phillips | 774e1b5 | 2006-11-01 00:10:40 -0600 | [diff] [blame] | 293 | { |
Kim Phillips | 2141681 | 2007-08-15 22:30:33 -0500 | [diff] [blame] | 294 | ft_cpu_setup(blob, bd); |
| 295 | #ifdef CONFIG_PCI |
| 296 | ft_pci_setup(blob, bd); |
| 297 | #endif |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 298 | |
| 299 | return 0; |
Kim Phillips | 774e1b5 | 2006-11-01 00:10:40 -0600 | [diff] [blame] | 300 | } |
| 301 | #endif |