| Simon Glass | dc79691 | 2019-12-08 17:32:10 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2017 Intel Corporation. |
| 4 | * Take from coreboot project file of the same name |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/intel_regs.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/systemagent.h> |
| 11 | |
| 12 | void enable_bios_reset_cpl(void) |
| 13 | { |
| 14 | /* |
| 15 | * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU |
| 16 | * that BIOS has initialised memory and power management |
| 17 | * |
| 18 | * The FSP-S does not do this. If we leave this as zero then I believe |
| 19 | * the power-aware interrupts don't work in Linux, and CPU 0 always gets |
| 20 | * the interrupt. |
| 21 | */ |
| 22 | setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); |
| 23 | } |