Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright © 2010-2015 Broadcom Corporation |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <common.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <memalign.h> |
| 18 | #include <nand.h> |
| 19 | #include <clk.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 20 | #include <dm/device_compat.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 21 | #include <dm/devres.h> |
Simon Glass | c06c1be | 2020-05-10 11:40:08 -0600 | [diff] [blame] | 22 | #include <linux/bug.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 23 | #include <linux/err.h> |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 24 | #include <linux/ioport.h> |
| 25 | #include <linux/completion.h> |
| 26 | #include <linux/errno.h> |
| 27 | #include <linux/log2.h> |
| 28 | #include <asm/processor.h> |
| 29 | #include <dm.h> |
| 30 | |
| 31 | #include "brcmnand.h" |
| 32 | #include "brcmnand_compat.h" |
| 33 | |
| 34 | /* |
| 35 | * This flag controls if WP stays on between erase/write commands to mitigate |
| 36 | * flash corruption due to power glitches. Values: |
| 37 | * 0: NAND_WP is not used or not available |
| 38 | * 1: NAND_WP is set by default, cleared for erase/write operations |
| 39 | * 2: NAND_WP is always cleared |
| 40 | */ |
| 41 | static int wp_on = 1; |
| 42 | module_param(wp_on, int, 0444); |
| 43 | |
| 44 | /*********************************************************************** |
| 45 | * Definitions |
| 46 | ***********************************************************************/ |
| 47 | |
| 48 | #define DRV_NAME "brcmnand" |
| 49 | |
| 50 | #define CMD_NULL 0x00 |
| 51 | #define CMD_PAGE_READ 0x01 |
| 52 | #define CMD_SPARE_AREA_READ 0x02 |
| 53 | #define CMD_STATUS_READ 0x03 |
| 54 | #define CMD_PROGRAM_PAGE 0x04 |
| 55 | #define CMD_PROGRAM_SPARE_AREA 0x05 |
| 56 | #define CMD_COPY_BACK 0x06 |
| 57 | #define CMD_DEVICE_ID_READ 0x07 |
| 58 | #define CMD_BLOCK_ERASE 0x08 |
| 59 | #define CMD_FLASH_RESET 0x09 |
| 60 | #define CMD_BLOCKS_LOCK 0x0a |
| 61 | #define CMD_BLOCKS_LOCK_DOWN 0x0b |
| 62 | #define CMD_BLOCKS_UNLOCK 0x0c |
| 63 | #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d |
| 64 | #define CMD_PARAMETER_READ 0x0e |
| 65 | #define CMD_PARAMETER_CHANGE_COL 0x0f |
| 66 | #define CMD_LOW_LEVEL_OP 0x10 |
| 67 | |
| 68 | struct brcm_nand_dma_desc { |
| 69 | u32 next_desc; |
| 70 | u32 next_desc_ext; |
| 71 | u32 cmd_irq; |
| 72 | u32 dram_addr; |
| 73 | u32 dram_addr_ext; |
| 74 | u32 tfr_len; |
| 75 | u32 total_len; |
| 76 | u32 flash_addr; |
| 77 | u32 flash_addr_ext; |
| 78 | u32 cs; |
| 79 | u32 pad2[5]; |
| 80 | u32 status_valid; |
| 81 | } __packed; |
| 82 | |
| 83 | /* Bitfields for brcm_nand_dma_desc::status_valid */ |
| 84 | #define FLASH_DMA_ECC_ERROR (1 << 8) |
| 85 | #define FLASH_DMA_CORR_ERROR (1 << 9) |
| 86 | |
| 87 | /* 512B flash cache in the NAND controller HW */ |
| 88 | #define FC_SHIFT 9U |
| 89 | #define FC_BYTES 512U |
| 90 | #define FC_WORDS (FC_BYTES >> 2) |
| 91 | |
| 92 | #define BRCMNAND_MIN_PAGESIZE 512 |
| 93 | #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024) |
| 94 | #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024) |
| 95 | |
| 96 | #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY) |
| 97 | #define NAND_POLL_STATUS_TIMEOUT_MS 100 |
| 98 | |
| 99 | /* Controller feature flags */ |
| 100 | enum { |
| 101 | BRCMNAND_HAS_1K_SECTORS = BIT(0), |
| 102 | BRCMNAND_HAS_PREFETCH = BIT(1), |
| 103 | BRCMNAND_HAS_CACHE_MODE = BIT(2), |
| 104 | BRCMNAND_HAS_WP = BIT(3), |
| 105 | }; |
| 106 | |
| 107 | struct brcmnand_controller { |
| 108 | #ifndef __UBOOT__ |
| 109 | struct device *dev; |
| 110 | #else |
| 111 | struct udevice *dev; |
| 112 | #endif /* __UBOOT__ */ |
| 113 | struct nand_hw_control controller; |
| 114 | void __iomem *nand_base; |
| 115 | void __iomem *nand_fc; /* flash cache */ |
| 116 | void __iomem *flash_dma_base; |
| 117 | unsigned int irq; |
| 118 | unsigned int dma_irq; |
| 119 | int nand_version; |
Philippe Reynes | 7f28cf6 | 2019-03-15 15:14:37 +0100 | [diff] [blame] | 120 | int parameter_page_big_endian; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 121 | |
| 122 | /* Some SoCs provide custom interrupt status register(s) */ |
| 123 | struct brcmnand_soc *soc; |
| 124 | |
| 125 | /* Some SoCs have a gateable clock for the controller */ |
| 126 | struct clk *clk; |
| 127 | |
| 128 | int cmd_pending; |
| 129 | bool dma_pending; |
| 130 | struct completion done; |
| 131 | struct completion dma_done; |
| 132 | |
| 133 | /* List of NAND hosts (one for each chip-select) */ |
| 134 | struct list_head host_list; |
| 135 | |
| 136 | struct brcm_nand_dma_desc *dma_desc; |
| 137 | dma_addr_t dma_pa; |
| 138 | |
| 139 | /* in-memory cache of the FLASH_CACHE, used only for some commands */ |
| 140 | u8 flash_cache[FC_BYTES]; |
| 141 | |
| 142 | /* Controller revision details */ |
| 143 | const u16 *reg_offsets; |
| 144 | unsigned int reg_spacing; /* between CS1, CS2, ... regs */ |
| 145 | const u8 *cs_offsets; /* within each chip-select */ |
| 146 | const u8 *cs0_offsets; /* within CS0, if different */ |
| 147 | unsigned int max_block_size; |
| 148 | const unsigned int *block_sizes; |
| 149 | unsigned int max_page_size; |
| 150 | const unsigned int *page_sizes; |
| 151 | unsigned int max_oob; |
| 152 | u32 features; |
| 153 | |
| 154 | /* for low-power standby/resume only */ |
| 155 | u32 nand_cs_nand_select; |
| 156 | u32 nand_cs_nand_xor; |
| 157 | u32 corr_stat_threshold; |
| 158 | u32 flash_dma_mode; |
| 159 | }; |
| 160 | |
| 161 | struct brcmnand_cfg { |
| 162 | u64 device_size; |
| 163 | unsigned int block_size; |
| 164 | unsigned int page_size; |
| 165 | unsigned int spare_area_size; |
| 166 | unsigned int device_width; |
| 167 | unsigned int col_adr_bytes; |
| 168 | unsigned int blk_adr_bytes; |
| 169 | unsigned int ful_adr_bytes; |
| 170 | unsigned int sector_size_1k; |
| 171 | unsigned int ecc_level; |
| 172 | /* use for low-power standby/resume only */ |
| 173 | u32 acc_control; |
| 174 | u32 config; |
| 175 | u32 config_ext; |
| 176 | u32 timing_1; |
| 177 | u32 timing_2; |
| 178 | }; |
| 179 | |
| 180 | struct brcmnand_host { |
| 181 | struct list_head node; |
| 182 | |
| 183 | struct nand_chip chip; |
| 184 | #ifndef __UBOOT__ |
| 185 | struct platform_device *pdev; |
| 186 | #else |
| 187 | struct udevice *pdev; |
| 188 | #endif /* __UBOOT__ */ |
| 189 | int cs; |
| 190 | |
| 191 | unsigned int last_cmd; |
| 192 | unsigned int last_byte; |
| 193 | u64 last_addr; |
| 194 | struct brcmnand_cfg hwcfg; |
| 195 | struct brcmnand_controller *ctrl; |
| 196 | }; |
| 197 | |
| 198 | enum brcmnand_reg { |
| 199 | BRCMNAND_CMD_START = 0, |
| 200 | BRCMNAND_CMD_EXT_ADDRESS, |
| 201 | BRCMNAND_CMD_ADDRESS, |
| 202 | BRCMNAND_INTFC_STATUS, |
| 203 | BRCMNAND_CS_SELECT, |
| 204 | BRCMNAND_CS_XOR, |
| 205 | BRCMNAND_LL_OP, |
| 206 | BRCMNAND_CS0_BASE, |
| 207 | BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */ |
| 208 | BRCMNAND_CORR_THRESHOLD, |
| 209 | BRCMNAND_CORR_THRESHOLD_EXT, |
| 210 | BRCMNAND_UNCORR_COUNT, |
| 211 | BRCMNAND_CORR_COUNT, |
| 212 | BRCMNAND_CORR_EXT_ADDR, |
| 213 | BRCMNAND_CORR_ADDR, |
| 214 | BRCMNAND_UNCORR_EXT_ADDR, |
| 215 | BRCMNAND_UNCORR_ADDR, |
| 216 | BRCMNAND_SEMAPHORE, |
| 217 | BRCMNAND_ID, |
| 218 | BRCMNAND_ID_EXT, |
| 219 | BRCMNAND_LL_RDATA, |
| 220 | BRCMNAND_OOB_READ_BASE, |
| 221 | BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */ |
| 222 | BRCMNAND_OOB_WRITE_BASE, |
| 223 | BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */ |
| 224 | BRCMNAND_FC_BASE, |
| 225 | }; |
| 226 | |
| 227 | /* BRCMNAND v4.0 */ |
| 228 | static const u16 brcmnand_regs_v40[] = { |
| 229 | [BRCMNAND_CMD_START] = 0x04, |
| 230 | [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, |
| 231 | [BRCMNAND_CMD_ADDRESS] = 0x0c, |
| 232 | [BRCMNAND_INTFC_STATUS] = 0x6c, |
| 233 | [BRCMNAND_CS_SELECT] = 0x14, |
| 234 | [BRCMNAND_CS_XOR] = 0x18, |
| 235 | [BRCMNAND_LL_OP] = 0x178, |
| 236 | [BRCMNAND_CS0_BASE] = 0x40, |
| 237 | [BRCMNAND_CS1_BASE] = 0xd0, |
| 238 | [BRCMNAND_CORR_THRESHOLD] = 0x84, |
| 239 | [BRCMNAND_CORR_THRESHOLD_EXT] = 0, |
| 240 | [BRCMNAND_UNCORR_COUNT] = 0, |
| 241 | [BRCMNAND_CORR_COUNT] = 0, |
| 242 | [BRCMNAND_CORR_EXT_ADDR] = 0x70, |
| 243 | [BRCMNAND_CORR_ADDR] = 0x74, |
| 244 | [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, |
| 245 | [BRCMNAND_UNCORR_ADDR] = 0x7c, |
| 246 | [BRCMNAND_SEMAPHORE] = 0x58, |
| 247 | [BRCMNAND_ID] = 0x60, |
| 248 | [BRCMNAND_ID_EXT] = 0x64, |
| 249 | [BRCMNAND_LL_RDATA] = 0x17c, |
| 250 | [BRCMNAND_OOB_READ_BASE] = 0x20, |
| 251 | [BRCMNAND_OOB_READ_10_BASE] = 0x130, |
| 252 | [BRCMNAND_OOB_WRITE_BASE] = 0x30, |
| 253 | [BRCMNAND_OOB_WRITE_10_BASE] = 0, |
| 254 | [BRCMNAND_FC_BASE] = 0x200, |
| 255 | }; |
| 256 | |
| 257 | /* BRCMNAND v5.0 */ |
| 258 | static const u16 brcmnand_regs_v50[] = { |
| 259 | [BRCMNAND_CMD_START] = 0x04, |
| 260 | [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, |
| 261 | [BRCMNAND_CMD_ADDRESS] = 0x0c, |
| 262 | [BRCMNAND_INTFC_STATUS] = 0x6c, |
| 263 | [BRCMNAND_CS_SELECT] = 0x14, |
| 264 | [BRCMNAND_CS_XOR] = 0x18, |
| 265 | [BRCMNAND_LL_OP] = 0x178, |
| 266 | [BRCMNAND_CS0_BASE] = 0x40, |
| 267 | [BRCMNAND_CS1_BASE] = 0xd0, |
| 268 | [BRCMNAND_CORR_THRESHOLD] = 0x84, |
| 269 | [BRCMNAND_CORR_THRESHOLD_EXT] = 0, |
| 270 | [BRCMNAND_UNCORR_COUNT] = 0, |
| 271 | [BRCMNAND_CORR_COUNT] = 0, |
| 272 | [BRCMNAND_CORR_EXT_ADDR] = 0x70, |
| 273 | [BRCMNAND_CORR_ADDR] = 0x74, |
| 274 | [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, |
| 275 | [BRCMNAND_UNCORR_ADDR] = 0x7c, |
| 276 | [BRCMNAND_SEMAPHORE] = 0x58, |
| 277 | [BRCMNAND_ID] = 0x60, |
| 278 | [BRCMNAND_ID_EXT] = 0x64, |
| 279 | [BRCMNAND_LL_RDATA] = 0x17c, |
| 280 | [BRCMNAND_OOB_READ_BASE] = 0x20, |
| 281 | [BRCMNAND_OOB_READ_10_BASE] = 0x130, |
| 282 | [BRCMNAND_OOB_WRITE_BASE] = 0x30, |
| 283 | [BRCMNAND_OOB_WRITE_10_BASE] = 0x140, |
| 284 | [BRCMNAND_FC_BASE] = 0x200, |
| 285 | }; |
| 286 | |
| 287 | /* BRCMNAND v6.0 - v7.1 */ |
| 288 | static const u16 brcmnand_regs_v60[] = { |
| 289 | [BRCMNAND_CMD_START] = 0x04, |
| 290 | [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, |
| 291 | [BRCMNAND_CMD_ADDRESS] = 0x0c, |
| 292 | [BRCMNAND_INTFC_STATUS] = 0x14, |
| 293 | [BRCMNAND_CS_SELECT] = 0x18, |
| 294 | [BRCMNAND_CS_XOR] = 0x1c, |
| 295 | [BRCMNAND_LL_OP] = 0x20, |
| 296 | [BRCMNAND_CS0_BASE] = 0x50, |
| 297 | [BRCMNAND_CS1_BASE] = 0, |
| 298 | [BRCMNAND_CORR_THRESHOLD] = 0xc0, |
| 299 | [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4, |
| 300 | [BRCMNAND_UNCORR_COUNT] = 0xfc, |
| 301 | [BRCMNAND_CORR_COUNT] = 0x100, |
| 302 | [BRCMNAND_CORR_EXT_ADDR] = 0x10c, |
| 303 | [BRCMNAND_CORR_ADDR] = 0x110, |
| 304 | [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, |
| 305 | [BRCMNAND_UNCORR_ADDR] = 0x118, |
| 306 | [BRCMNAND_SEMAPHORE] = 0x150, |
| 307 | [BRCMNAND_ID] = 0x194, |
| 308 | [BRCMNAND_ID_EXT] = 0x198, |
| 309 | [BRCMNAND_LL_RDATA] = 0x19c, |
| 310 | [BRCMNAND_OOB_READ_BASE] = 0x200, |
| 311 | [BRCMNAND_OOB_READ_10_BASE] = 0, |
| 312 | [BRCMNAND_OOB_WRITE_BASE] = 0x280, |
| 313 | [BRCMNAND_OOB_WRITE_10_BASE] = 0, |
| 314 | [BRCMNAND_FC_BASE] = 0x400, |
| 315 | }; |
| 316 | |
| 317 | /* BRCMNAND v7.1 */ |
| 318 | static const u16 brcmnand_regs_v71[] = { |
| 319 | [BRCMNAND_CMD_START] = 0x04, |
| 320 | [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, |
| 321 | [BRCMNAND_CMD_ADDRESS] = 0x0c, |
| 322 | [BRCMNAND_INTFC_STATUS] = 0x14, |
| 323 | [BRCMNAND_CS_SELECT] = 0x18, |
| 324 | [BRCMNAND_CS_XOR] = 0x1c, |
| 325 | [BRCMNAND_LL_OP] = 0x20, |
| 326 | [BRCMNAND_CS0_BASE] = 0x50, |
| 327 | [BRCMNAND_CS1_BASE] = 0, |
| 328 | [BRCMNAND_CORR_THRESHOLD] = 0xdc, |
| 329 | [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, |
| 330 | [BRCMNAND_UNCORR_COUNT] = 0xfc, |
| 331 | [BRCMNAND_CORR_COUNT] = 0x100, |
| 332 | [BRCMNAND_CORR_EXT_ADDR] = 0x10c, |
| 333 | [BRCMNAND_CORR_ADDR] = 0x110, |
| 334 | [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, |
| 335 | [BRCMNAND_UNCORR_ADDR] = 0x118, |
| 336 | [BRCMNAND_SEMAPHORE] = 0x150, |
| 337 | [BRCMNAND_ID] = 0x194, |
| 338 | [BRCMNAND_ID_EXT] = 0x198, |
| 339 | [BRCMNAND_LL_RDATA] = 0x19c, |
| 340 | [BRCMNAND_OOB_READ_BASE] = 0x200, |
| 341 | [BRCMNAND_OOB_READ_10_BASE] = 0, |
| 342 | [BRCMNAND_OOB_WRITE_BASE] = 0x280, |
| 343 | [BRCMNAND_OOB_WRITE_10_BASE] = 0, |
| 344 | [BRCMNAND_FC_BASE] = 0x400, |
| 345 | }; |
| 346 | |
| 347 | /* BRCMNAND v7.2 */ |
| 348 | static const u16 brcmnand_regs_v72[] = { |
| 349 | [BRCMNAND_CMD_START] = 0x04, |
| 350 | [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, |
| 351 | [BRCMNAND_CMD_ADDRESS] = 0x0c, |
| 352 | [BRCMNAND_INTFC_STATUS] = 0x14, |
| 353 | [BRCMNAND_CS_SELECT] = 0x18, |
| 354 | [BRCMNAND_CS_XOR] = 0x1c, |
| 355 | [BRCMNAND_LL_OP] = 0x20, |
| 356 | [BRCMNAND_CS0_BASE] = 0x50, |
| 357 | [BRCMNAND_CS1_BASE] = 0, |
| 358 | [BRCMNAND_CORR_THRESHOLD] = 0xdc, |
| 359 | [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, |
| 360 | [BRCMNAND_UNCORR_COUNT] = 0xfc, |
| 361 | [BRCMNAND_CORR_COUNT] = 0x100, |
| 362 | [BRCMNAND_CORR_EXT_ADDR] = 0x10c, |
| 363 | [BRCMNAND_CORR_ADDR] = 0x110, |
| 364 | [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, |
| 365 | [BRCMNAND_UNCORR_ADDR] = 0x118, |
| 366 | [BRCMNAND_SEMAPHORE] = 0x150, |
| 367 | [BRCMNAND_ID] = 0x194, |
| 368 | [BRCMNAND_ID_EXT] = 0x198, |
| 369 | [BRCMNAND_LL_RDATA] = 0x19c, |
| 370 | [BRCMNAND_OOB_READ_BASE] = 0x200, |
| 371 | [BRCMNAND_OOB_READ_10_BASE] = 0, |
| 372 | [BRCMNAND_OOB_WRITE_BASE] = 0x400, |
| 373 | [BRCMNAND_OOB_WRITE_10_BASE] = 0, |
| 374 | [BRCMNAND_FC_BASE] = 0x600, |
| 375 | }; |
| 376 | |
| 377 | enum brcmnand_cs_reg { |
| 378 | BRCMNAND_CS_CFG_EXT = 0, |
| 379 | BRCMNAND_CS_CFG, |
| 380 | BRCMNAND_CS_ACC_CONTROL, |
| 381 | BRCMNAND_CS_TIMING1, |
| 382 | BRCMNAND_CS_TIMING2, |
| 383 | }; |
| 384 | |
| 385 | /* Per chip-select offsets for v7.1 */ |
| 386 | static const u8 brcmnand_cs_offsets_v71[] = { |
| 387 | [BRCMNAND_CS_ACC_CONTROL] = 0x00, |
| 388 | [BRCMNAND_CS_CFG_EXT] = 0x04, |
| 389 | [BRCMNAND_CS_CFG] = 0x08, |
| 390 | [BRCMNAND_CS_TIMING1] = 0x0c, |
| 391 | [BRCMNAND_CS_TIMING2] = 0x10, |
| 392 | }; |
| 393 | |
| 394 | /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */ |
| 395 | static const u8 brcmnand_cs_offsets[] = { |
| 396 | [BRCMNAND_CS_ACC_CONTROL] = 0x00, |
| 397 | [BRCMNAND_CS_CFG_EXT] = 0x04, |
| 398 | [BRCMNAND_CS_CFG] = 0x04, |
| 399 | [BRCMNAND_CS_TIMING1] = 0x08, |
| 400 | [BRCMNAND_CS_TIMING2] = 0x0c, |
| 401 | }; |
| 402 | |
| 403 | /* Per chip-select offset for <= v5.0 on CS0 only */ |
| 404 | static const u8 brcmnand_cs_offsets_cs0[] = { |
| 405 | [BRCMNAND_CS_ACC_CONTROL] = 0x00, |
| 406 | [BRCMNAND_CS_CFG_EXT] = 0x08, |
| 407 | [BRCMNAND_CS_CFG] = 0x08, |
| 408 | [BRCMNAND_CS_TIMING1] = 0x10, |
| 409 | [BRCMNAND_CS_TIMING2] = 0x14, |
| 410 | }; |
| 411 | |
| 412 | /* |
| 413 | * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had |
| 414 | * one config register, but once the bitfields overflowed, newer controllers |
| 415 | * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around. |
| 416 | */ |
| 417 | enum { |
| 418 | CFG_BLK_ADR_BYTES_SHIFT = 8, |
| 419 | CFG_COL_ADR_BYTES_SHIFT = 12, |
| 420 | CFG_FUL_ADR_BYTES_SHIFT = 16, |
| 421 | CFG_BUS_WIDTH_SHIFT = 23, |
| 422 | CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT), |
| 423 | CFG_DEVICE_SIZE_SHIFT = 24, |
| 424 | |
| 425 | /* Only for pre-v7.1 (with no CFG_EXT register) */ |
| 426 | CFG_PAGE_SIZE_SHIFT = 20, |
| 427 | CFG_BLK_SIZE_SHIFT = 28, |
| 428 | |
| 429 | /* Only for v7.1+ (with CFG_EXT register) */ |
| 430 | CFG_EXT_PAGE_SIZE_SHIFT = 0, |
| 431 | CFG_EXT_BLK_SIZE_SHIFT = 4, |
| 432 | }; |
| 433 | |
| 434 | /* BRCMNAND_INTFC_STATUS */ |
| 435 | enum { |
| 436 | INTFC_FLASH_STATUS = GENMASK(7, 0), |
| 437 | |
| 438 | INTFC_ERASED = BIT(27), |
| 439 | INTFC_OOB_VALID = BIT(28), |
| 440 | INTFC_CACHE_VALID = BIT(29), |
| 441 | INTFC_FLASH_READY = BIT(30), |
| 442 | INTFC_CTLR_READY = BIT(31), |
| 443 | }; |
| 444 | |
| 445 | static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) |
| 446 | { |
| 447 | return brcmnand_readl(ctrl->nand_base + offs); |
| 448 | } |
| 449 | |
| 450 | static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, |
| 451 | u32 val) |
| 452 | { |
| 453 | brcmnand_writel(val, ctrl->nand_base + offs); |
| 454 | } |
| 455 | |
| 456 | static int brcmnand_revision_init(struct brcmnand_controller *ctrl) |
| 457 | { |
| 458 | static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 }; |
| 459 | static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 }; |
| 460 | static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 }; |
| 461 | |
| 462 | ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; |
| 463 | |
| 464 | /* Only support v4.0+? */ |
| 465 | if (ctrl->nand_version < 0x0400) { |
| 466 | dev_err(ctrl->dev, "version %#x not supported\n", |
| 467 | ctrl->nand_version); |
| 468 | return -ENODEV; |
| 469 | } |
| 470 | |
| 471 | /* Register offsets */ |
| 472 | if (ctrl->nand_version >= 0x0702) |
| 473 | ctrl->reg_offsets = brcmnand_regs_v72; |
| 474 | else if (ctrl->nand_version >= 0x0701) |
| 475 | ctrl->reg_offsets = brcmnand_regs_v71; |
| 476 | else if (ctrl->nand_version >= 0x0600) |
| 477 | ctrl->reg_offsets = brcmnand_regs_v60; |
| 478 | else if (ctrl->nand_version >= 0x0500) |
| 479 | ctrl->reg_offsets = brcmnand_regs_v50; |
| 480 | else if (ctrl->nand_version >= 0x0400) |
| 481 | ctrl->reg_offsets = brcmnand_regs_v40; |
| 482 | |
| 483 | /* Chip-select stride */ |
| 484 | if (ctrl->nand_version >= 0x0701) |
| 485 | ctrl->reg_spacing = 0x14; |
| 486 | else |
| 487 | ctrl->reg_spacing = 0x10; |
| 488 | |
| 489 | /* Per chip-select registers */ |
| 490 | if (ctrl->nand_version >= 0x0701) { |
| 491 | ctrl->cs_offsets = brcmnand_cs_offsets_v71; |
| 492 | } else { |
| 493 | ctrl->cs_offsets = brcmnand_cs_offsets; |
| 494 | |
| 495 | /* v5.0 and earlier has a different CS0 offset layout */ |
| 496 | if (ctrl->nand_version <= 0x0500) |
| 497 | ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; |
| 498 | } |
| 499 | |
| 500 | /* Page / block sizes */ |
| 501 | if (ctrl->nand_version >= 0x0701) { |
| 502 | /* >= v7.1 use nice power-of-2 values! */ |
| 503 | ctrl->max_page_size = 16 * 1024; |
| 504 | ctrl->max_block_size = 2 * 1024 * 1024; |
| 505 | } else { |
| 506 | ctrl->page_sizes = page_sizes; |
| 507 | if (ctrl->nand_version >= 0x0600) |
| 508 | ctrl->block_sizes = block_sizes_v6; |
| 509 | else |
| 510 | ctrl->block_sizes = block_sizes_v4; |
| 511 | |
| 512 | if (ctrl->nand_version < 0x0400) { |
| 513 | ctrl->max_page_size = 4096; |
| 514 | ctrl->max_block_size = 512 * 1024; |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | /* Maximum spare area sector size (per 512B) */ |
| 519 | if (ctrl->nand_version >= 0x0702) |
| 520 | ctrl->max_oob = 128; |
| 521 | else if (ctrl->nand_version >= 0x0600) |
| 522 | ctrl->max_oob = 64; |
| 523 | else if (ctrl->nand_version >= 0x0500) |
| 524 | ctrl->max_oob = 32; |
| 525 | else |
| 526 | ctrl->max_oob = 16; |
| 527 | |
| 528 | /* v6.0 and newer (except v6.1) have prefetch support */ |
| 529 | if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) |
| 530 | ctrl->features |= BRCMNAND_HAS_PREFETCH; |
| 531 | |
| 532 | /* |
| 533 | * v6.x has cache mode, but it's implemented differently. Ignore it for |
| 534 | * now. |
| 535 | */ |
| 536 | if (ctrl->nand_version >= 0x0700) |
| 537 | ctrl->features |= BRCMNAND_HAS_CACHE_MODE; |
| 538 | |
| 539 | if (ctrl->nand_version >= 0x0500) |
| 540 | ctrl->features |= BRCMNAND_HAS_1K_SECTORS; |
| 541 | |
| 542 | if (ctrl->nand_version >= 0x0700) |
| 543 | ctrl->features |= BRCMNAND_HAS_WP; |
| 544 | #ifndef __UBOOT__ |
| 545 | else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) |
| 546 | #else |
| 547 | else if (dev_read_bool(ctrl->dev, "brcm,nand-has-wp")) |
| 548 | #endif /* __UBOOT__ */ |
| 549 | ctrl->features |= BRCMNAND_HAS_WP; |
| 550 | |
| 551 | return 0; |
| 552 | } |
| 553 | |
| 554 | static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, |
| 555 | enum brcmnand_reg reg) |
| 556 | { |
| 557 | u16 offs = ctrl->reg_offsets[reg]; |
| 558 | |
| 559 | if (offs) |
| 560 | return nand_readreg(ctrl, offs); |
| 561 | else |
| 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl, |
| 566 | enum brcmnand_reg reg, u32 val) |
| 567 | { |
| 568 | u16 offs = ctrl->reg_offsets[reg]; |
| 569 | |
| 570 | if (offs) |
| 571 | nand_writereg(ctrl, offs, val); |
| 572 | } |
| 573 | |
| 574 | static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, |
| 575 | enum brcmnand_reg reg, u32 mask, unsigned |
| 576 | int shift, u32 val) |
| 577 | { |
| 578 | u32 tmp = brcmnand_read_reg(ctrl, reg); |
| 579 | |
| 580 | tmp &= ~mask; |
| 581 | tmp |= val << shift; |
| 582 | brcmnand_write_reg(ctrl, reg, tmp); |
| 583 | } |
| 584 | |
| 585 | static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) |
| 586 | { |
| 587 | return __raw_readl(ctrl->nand_fc + word * 4); |
| 588 | } |
| 589 | |
| 590 | static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, |
| 591 | int word, u32 val) |
| 592 | { |
| 593 | __raw_writel(val, ctrl->nand_fc + word * 4); |
| 594 | } |
| 595 | |
| 596 | static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, |
| 597 | enum brcmnand_cs_reg reg) |
| 598 | { |
| 599 | u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; |
| 600 | u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; |
| 601 | u8 cs_offs; |
| 602 | |
| 603 | if (cs == 0 && ctrl->cs0_offsets) |
| 604 | cs_offs = ctrl->cs0_offsets[reg]; |
| 605 | else |
| 606 | cs_offs = ctrl->cs_offsets[reg]; |
| 607 | |
| 608 | if (cs && offs_cs1) |
| 609 | return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; |
| 610 | |
| 611 | return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; |
| 612 | } |
| 613 | |
| 614 | static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl) |
| 615 | { |
| 616 | if (ctrl->nand_version < 0x0600) |
| 617 | return 1; |
| 618 | return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT); |
| 619 | } |
| 620 | |
| 621 | static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val) |
| 622 | { |
| 623 | struct brcmnand_controller *ctrl = host->ctrl; |
| 624 | unsigned int shift = 0, bits; |
| 625 | enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD; |
| 626 | int cs = host->cs; |
| 627 | |
| 628 | if (ctrl->nand_version >= 0x0702) |
| 629 | bits = 7; |
| 630 | else if (ctrl->nand_version >= 0x0600) |
| 631 | bits = 6; |
| 632 | else if (ctrl->nand_version >= 0x0500) |
| 633 | bits = 5; |
| 634 | else |
| 635 | bits = 4; |
| 636 | |
| 637 | if (ctrl->nand_version >= 0x0702) { |
| 638 | if (cs >= 4) |
| 639 | reg = BRCMNAND_CORR_THRESHOLD_EXT; |
| 640 | shift = (cs % 4) * bits; |
| 641 | } else if (ctrl->nand_version >= 0x0600) { |
| 642 | if (cs >= 5) |
| 643 | reg = BRCMNAND_CORR_THRESHOLD_EXT; |
| 644 | shift = (cs % 5) * bits; |
| 645 | } |
| 646 | brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); |
| 647 | } |
| 648 | |
| 649 | static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) |
| 650 | { |
| 651 | if (ctrl->nand_version < 0x0602) |
| 652 | return 24; |
| 653 | return 0; |
| 654 | } |
| 655 | |
| 656 | /*********************************************************************** |
| 657 | * NAND ACC CONTROL bitfield |
| 658 | * |
| 659 | * Some bits have remained constant throughout hardware revision, while |
| 660 | * others have shifted around. |
| 661 | ***********************************************************************/ |
| 662 | |
| 663 | /* Constant for all versions (where supported) */ |
| 664 | enum { |
| 665 | /* See BRCMNAND_HAS_CACHE_MODE */ |
| 666 | ACC_CONTROL_CACHE_MODE = BIT(22), |
| 667 | |
| 668 | /* See BRCMNAND_HAS_PREFETCH */ |
| 669 | ACC_CONTROL_PREFETCH = BIT(23), |
| 670 | |
| 671 | ACC_CONTROL_PAGE_HIT = BIT(24), |
| 672 | ACC_CONTROL_WR_PREEMPT = BIT(25), |
| 673 | ACC_CONTROL_PARTIAL_PAGE = BIT(26), |
| 674 | ACC_CONTROL_RD_ERASED = BIT(27), |
| 675 | ACC_CONTROL_FAST_PGM_RDIN = BIT(28), |
| 676 | ACC_CONTROL_WR_ECC = BIT(30), |
| 677 | ACC_CONTROL_RD_ECC = BIT(31), |
| 678 | }; |
| 679 | |
| 680 | static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) |
| 681 | { |
| 682 | if (ctrl->nand_version >= 0x0702) |
| 683 | return GENMASK(7, 0); |
| 684 | else if (ctrl->nand_version >= 0x0600) |
| 685 | return GENMASK(6, 0); |
| 686 | else |
| 687 | return GENMASK(5, 0); |
| 688 | } |
| 689 | |
| 690 | #define NAND_ACC_CONTROL_ECC_SHIFT 16 |
| 691 | #define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13 |
| 692 | |
| 693 | static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) |
| 694 | { |
| 695 | u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; |
| 696 | |
| 697 | mask <<= NAND_ACC_CONTROL_ECC_SHIFT; |
| 698 | |
| 699 | /* v7.2 includes additional ECC levels */ |
| 700 | if (ctrl->nand_version >= 0x0702) |
| 701 | mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT; |
| 702 | |
| 703 | return mask; |
| 704 | } |
| 705 | |
| 706 | static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) |
| 707 | { |
| 708 | struct brcmnand_controller *ctrl = host->ctrl; |
| 709 | u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); |
| 710 | u32 acc_control = nand_readreg(ctrl, offs); |
| 711 | u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC; |
| 712 | |
| 713 | if (en) { |
| 714 | acc_control |= ecc_flags; /* enable RD/WR ECC */ |
| 715 | acc_control |= host->hwcfg.ecc_level |
| 716 | << NAND_ACC_CONTROL_ECC_SHIFT; |
| 717 | } else { |
| 718 | acc_control &= ~ecc_flags; /* disable RD/WR ECC */ |
| 719 | acc_control &= ~brcmnand_ecc_level_mask(ctrl); |
| 720 | } |
| 721 | |
| 722 | nand_writereg(ctrl, offs, acc_control); |
| 723 | } |
| 724 | |
| 725 | static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) |
| 726 | { |
| 727 | if (ctrl->nand_version >= 0x0702) |
| 728 | return 9; |
| 729 | else if (ctrl->nand_version >= 0x0600) |
| 730 | return 7; |
| 731 | else if (ctrl->nand_version >= 0x0500) |
| 732 | return 6; |
| 733 | else |
| 734 | return -1; |
| 735 | } |
| 736 | |
| 737 | static int brcmnand_get_sector_size_1k(struct brcmnand_host *host) |
| 738 | { |
| 739 | struct brcmnand_controller *ctrl = host->ctrl; |
| 740 | int shift = brcmnand_sector_1k_shift(ctrl); |
| 741 | u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, |
| 742 | BRCMNAND_CS_ACC_CONTROL); |
| 743 | |
| 744 | if (shift < 0) |
| 745 | return 0; |
| 746 | |
| 747 | return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1; |
| 748 | } |
| 749 | |
| 750 | static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val) |
| 751 | { |
| 752 | struct brcmnand_controller *ctrl = host->ctrl; |
| 753 | int shift = brcmnand_sector_1k_shift(ctrl); |
| 754 | u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, |
| 755 | BRCMNAND_CS_ACC_CONTROL); |
| 756 | u32 tmp; |
| 757 | |
| 758 | if (shift < 0) |
| 759 | return; |
| 760 | |
| 761 | tmp = nand_readreg(ctrl, acc_control_offs); |
| 762 | tmp &= ~(1 << shift); |
| 763 | tmp |= (!!val) << shift; |
| 764 | nand_writereg(ctrl, acc_control_offs, tmp); |
| 765 | } |
| 766 | |
| 767 | /*********************************************************************** |
| 768 | * CS_NAND_SELECT |
| 769 | ***********************************************************************/ |
| 770 | |
| 771 | enum { |
| 772 | CS_SELECT_NAND_WP = BIT(29), |
| 773 | CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30), |
| 774 | }; |
| 775 | |
| 776 | static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, |
| 777 | u32 mask, u32 expected_val, |
| 778 | unsigned long timeout_ms) |
| 779 | { |
| 780 | #ifndef __UBOOT__ |
| 781 | unsigned long limit; |
| 782 | u32 val; |
| 783 | |
| 784 | if (!timeout_ms) |
| 785 | timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS; |
| 786 | |
| 787 | limit = jiffies + msecs_to_jiffies(timeout_ms); |
| 788 | do { |
| 789 | val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); |
| 790 | if ((val & mask) == expected_val) |
| 791 | return 0; |
| 792 | |
| 793 | cpu_relax(); |
| 794 | } while (time_after(limit, jiffies)); |
| 795 | #else |
| 796 | unsigned long base, limit; |
| 797 | u32 val; |
| 798 | |
| 799 | if (!timeout_ms) |
| 800 | timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS; |
| 801 | |
| 802 | base = get_timer(0); |
| 803 | limit = CONFIG_SYS_HZ * timeout_ms / 1000; |
| 804 | do { |
| 805 | val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); |
| 806 | if ((val & mask) == expected_val) |
| 807 | return 0; |
| 808 | |
| 809 | cpu_relax(); |
| 810 | } while (get_timer(base) < limit); |
| 811 | #endif /* __UBOOT__ */ |
| 812 | |
| 813 | dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", |
| 814 | expected_val, val & mask); |
| 815 | |
| 816 | return -ETIMEDOUT; |
| 817 | } |
| 818 | |
| 819 | static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) |
| 820 | { |
| 821 | u32 val = en ? CS_SELECT_NAND_WP : 0; |
| 822 | |
| 823 | brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); |
| 824 | } |
| 825 | |
| 826 | /*********************************************************************** |
| 827 | * Flash DMA |
| 828 | ***********************************************************************/ |
| 829 | |
| 830 | enum flash_dma_reg { |
| 831 | FLASH_DMA_REVISION = 0x00, |
| 832 | FLASH_DMA_FIRST_DESC = 0x04, |
| 833 | FLASH_DMA_FIRST_DESC_EXT = 0x08, |
| 834 | FLASH_DMA_CTRL = 0x0c, |
| 835 | FLASH_DMA_MODE = 0x10, |
| 836 | FLASH_DMA_STATUS = 0x14, |
| 837 | FLASH_DMA_INTERRUPT_DESC = 0x18, |
| 838 | FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c, |
| 839 | FLASH_DMA_ERROR_STATUS = 0x20, |
| 840 | FLASH_DMA_CURRENT_DESC = 0x24, |
| 841 | FLASH_DMA_CURRENT_DESC_EXT = 0x28, |
| 842 | }; |
| 843 | |
| 844 | static inline bool has_flash_dma(struct brcmnand_controller *ctrl) |
| 845 | { |
| 846 | return ctrl->flash_dma_base; |
| 847 | } |
| 848 | |
| 849 | static inline bool flash_dma_buf_ok(const void *buf) |
| 850 | { |
| 851 | #ifndef __UBOOT__ |
| 852 | return buf && !is_vmalloc_addr(buf) && |
| 853 | likely(IS_ALIGNED((uintptr_t)buf, 4)); |
| 854 | #else |
| 855 | return buf && likely(IS_ALIGNED((uintptr_t)buf, 4)); |
| 856 | #endif /* __UBOOT__ */ |
| 857 | } |
| 858 | |
| 859 | static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs, |
| 860 | u32 val) |
| 861 | { |
| 862 | brcmnand_writel(val, ctrl->flash_dma_base + offs); |
| 863 | } |
| 864 | |
| 865 | static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs) |
| 866 | { |
| 867 | return brcmnand_readl(ctrl->flash_dma_base + offs); |
| 868 | } |
| 869 | |
| 870 | /* Low-level operation types: command, address, write, or read */ |
| 871 | enum brcmnand_llop_type { |
| 872 | LL_OP_CMD, |
| 873 | LL_OP_ADDR, |
| 874 | LL_OP_WR, |
| 875 | LL_OP_RD, |
| 876 | }; |
| 877 | |
| 878 | /*********************************************************************** |
| 879 | * Internal support functions |
| 880 | ***********************************************************************/ |
| 881 | |
| 882 | static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl, |
| 883 | struct brcmnand_cfg *cfg) |
| 884 | { |
| 885 | if (ctrl->nand_version <= 0x0701) |
| 886 | return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && |
| 887 | cfg->ecc_level == 15; |
| 888 | else |
| 889 | return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && |
| 890 | cfg->ecc_level == 15) || |
| 891 | (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); |
| 892 | } |
| 893 | |
| 894 | /* |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 895 | * Returns a nand_ecclayout strucutre for the given layout/configuration. |
| 896 | * Returns NULL on failure. |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 897 | */ |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 898 | static struct nand_ecclayout *brcmnand_create_layout(int ecc_level, |
| 899 | struct brcmnand_host *host) |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 900 | { |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 901 | struct brcmnand_cfg *cfg = &host->hwcfg; |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 902 | int i, j; |
| 903 | struct nand_ecclayout *layout; |
| 904 | int req; |
| 905 | int sectors; |
| 906 | int sas; |
| 907 | int idx1, idx2; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 908 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 909 | #ifndef __UBOOT__ |
| 910 | layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL); |
| 911 | #else |
| 912 | layout = devm_kzalloc(host->pdev, sizeof(*layout), GFP_KERNEL); |
| 913 | #endif |
| 914 | if (!layout) |
| 915 | return NULL; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 916 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 917 | sectors = cfg->page_size / (512 << cfg->sector_size_1k); |
| 918 | sas = cfg->spare_area_size << cfg->sector_size_1k; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 919 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 920 | /* Hamming */ |
| 921 | if (is_hamming_ecc(host->ctrl, cfg)) { |
| 922 | for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) { |
| 923 | /* First sector of each page may have BBI */ |
| 924 | if (i == 0) { |
| 925 | layout->oobfree[idx2].offset = i * sas + 1; |
| 926 | /* Small-page NAND use byte 6 for BBI */ |
| 927 | if (cfg->page_size == 512) |
| 928 | layout->oobfree[idx2].offset--; |
| 929 | layout->oobfree[idx2].length = 5; |
| 930 | } else { |
| 931 | layout->oobfree[idx2].offset = i * sas; |
| 932 | layout->oobfree[idx2].length = 6; |
| 933 | } |
| 934 | idx2++; |
| 935 | layout->eccpos[idx1++] = i * sas + 6; |
| 936 | layout->eccpos[idx1++] = i * sas + 7; |
| 937 | layout->eccpos[idx1++] = i * sas + 8; |
| 938 | layout->oobfree[idx2].offset = i * sas + 9; |
| 939 | layout->oobfree[idx2].length = 7; |
| 940 | idx2++; |
| 941 | /* Leave zero-terminated entry for OOBFREE */ |
| 942 | if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE || |
| 943 | idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1) |
| 944 | break; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 945 | } |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 946 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 947 | return layout; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 948 | } |
| 949 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 950 | /* |
| 951 | * CONTROLLER_VERSION: |
| 952 | * < v5.0: ECC_REQ = ceil(BCH_T * 13/8) |
| 953 | * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8) |
| 954 | * But we will just be conservative. |
| 955 | */ |
| 956 | req = DIV_ROUND_UP(ecc_level * 14, 8); |
| 957 | if (req >= sas) { |
| 958 | dev_err(&host->pdev->dev, |
| 959 | "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", |
| 960 | req, sas); |
| 961 | return NULL; |
| 962 | } |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 963 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 964 | layout->eccbytes = req * sectors; |
| 965 | for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) { |
| 966 | for (j = sas - req; j < sas && idx1 < |
| 967 | MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++) |
| 968 | layout->eccpos[idx1] = i * sas + j; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 969 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 970 | /* First sector of each page may have BBI */ |
| 971 | if (i == 0) { |
| 972 | if (cfg->page_size == 512 && (sas - req >= 6)) { |
| 973 | /* Small-page NAND use byte 6 for BBI */ |
| 974 | layout->oobfree[idx2].offset = 0; |
| 975 | layout->oobfree[idx2].length = 5; |
| 976 | idx2++; |
| 977 | if (sas - req > 6) { |
| 978 | layout->oobfree[idx2].offset = 6; |
| 979 | layout->oobfree[idx2].length = |
| 980 | sas - req - 6; |
| 981 | idx2++; |
| 982 | } |
| 983 | } else if (sas > req + 1) { |
| 984 | layout->oobfree[idx2].offset = i * sas + 1; |
| 985 | layout->oobfree[idx2].length = sas - req - 1; |
| 986 | idx2++; |
| 987 | } |
| 988 | } else if (sas > req) { |
| 989 | layout->oobfree[idx2].offset = i * sas; |
| 990 | layout->oobfree[idx2].length = sas - req; |
| 991 | idx2++; |
| 992 | } |
| 993 | /* Leave zero-terminated entry for OOBFREE */ |
| 994 | if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE || |
| 995 | idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1) |
| 996 | break; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 997 | } |
| 998 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 999 | return layout; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1000 | } |
| 1001 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 1002 | static struct nand_ecclayout *brcmstb_choose_ecc_layout( |
| 1003 | struct brcmnand_host *host) |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1004 | { |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 1005 | struct nand_ecclayout *layout; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1006 | struct brcmnand_cfg *p = &host->hwcfg; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1007 | unsigned int ecc_level = p->ecc_level; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1008 | |
| 1009 | if (p->sector_size_1k) |
| 1010 | ecc_level <<= 1; |
| 1011 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 1012 | layout = brcmnand_create_layout(ecc_level, host); |
| 1013 | if (!layout) { |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1014 | dev_err(&host->pdev->dev, |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 1015 | "no proper ecc_layout for this NAND cfg\n"); |
| 1016 | return NULL; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1017 | } |
| 1018 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 1019 | return layout; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1020 | } |
| 1021 | |
| 1022 | static void brcmnand_wp(struct mtd_info *mtd, int wp) |
| 1023 | { |
| 1024 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 1025 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1026 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1027 | |
| 1028 | if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { |
| 1029 | static int old_wp = -1; |
| 1030 | int ret; |
| 1031 | |
| 1032 | if (old_wp != wp) { |
| 1033 | dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); |
| 1034 | old_wp = wp; |
| 1035 | } |
| 1036 | |
| 1037 | /* |
| 1038 | * make sure ctrl/flash ready before and after |
| 1039 | * changing state of #WP pin |
| 1040 | */ |
| 1041 | ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY | |
| 1042 | NAND_STATUS_READY, |
| 1043 | NAND_CTRL_RDY | |
| 1044 | NAND_STATUS_READY, 0); |
| 1045 | if (ret) |
| 1046 | return; |
| 1047 | |
| 1048 | brcmnand_set_wp(ctrl, wp); |
| 1049 | nand_status_op(chip, NULL); |
| 1050 | /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */ |
| 1051 | ret = bcmnand_ctrl_poll_status(ctrl, |
| 1052 | NAND_CTRL_RDY | |
| 1053 | NAND_STATUS_READY | |
| 1054 | NAND_STATUS_WP, |
| 1055 | NAND_CTRL_RDY | |
| 1056 | NAND_STATUS_READY | |
| 1057 | (wp ? 0 : NAND_STATUS_WP), 0); |
| 1058 | #ifndef __UBOOT__ |
| 1059 | if (ret) |
| 1060 | dev_err_ratelimited(&host->pdev->dev, |
| 1061 | "nand #WP expected %s\n", |
| 1062 | wp ? "on" : "off"); |
| 1063 | #else |
| 1064 | if (ret) |
| 1065 | dev_err(&host->pdev->dev, |
| 1066 | "nand #WP expected %s\n", |
| 1067 | wp ? "on" : "off"); |
| 1068 | #endif /* __UBOOT__ */ |
| 1069 | } |
| 1070 | } |
| 1071 | |
| 1072 | /* Helper functions for reading and writing OOB registers */ |
| 1073 | static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) |
| 1074 | { |
| 1075 | u16 offset0, offset10, reg_offs; |
| 1076 | |
| 1077 | offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; |
| 1078 | offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; |
| 1079 | |
| 1080 | if (offs >= ctrl->max_oob) |
| 1081 | return 0x77; |
| 1082 | |
| 1083 | if (offs >= 16 && offset10) |
| 1084 | reg_offs = offset10 + ((offs - 0x10) & ~0x03); |
| 1085 | else |
| 1086 | reg_offs = offset0 + (offs & ~0x03); |
| 1087 | |
| 1088 | return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); |
| 1089 | } |
| 1090 | |
| 1091 | static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, |
| 1092 | u32 data) |
| 1093 | { |
| 1094 | u16 offset0, offset10, reg_offs; |
| 1095 | |
| 1096 | offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; |
| 1097 | offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; |
| 1098 | |
| 1099 | if (offs >= ctrl->max_oob) |
| 1100 | return; |
| 1101 | |
| 1102 | if (offs >= 16 && offset10) |
| 1103 | reg_offs = offset10 + ((offs - 0x10) & ~0x03); |
| 1104 | else |
| 1105 | reg_offs = offset0 + (offs & ~0x03); |
| 1106 | |
| 1107 | nand_writereg(ctrl, reg_offs, data); |
| 1108 | } |
| 1109 | |
| 1110 | /* |
| 1111 | * read_oob_from_regs - read data from OOB registers |
| 1112 | * @ctrl: NAND controller |
| 1113 | * @i: sub-page sector index |
| 1114 | * @oob: buffer to read to |
| 1115 | * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) |
| 1116 | * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal |
| 1117 | */ |
| 1118 | static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, |
| 1119 | int sas, int sector_1k) |
| 1120 | { |
| 1121 | int tbytes = sas << sector_1k; |
| 1122 | int j; |
| 1123 | |
| 1124 | /* Adjust OOB values for 1K sector size */ |
| 1125 | if (sector_1k && (i & 0x01)) |
| 1126 | tbytes = max(0, tbytes - (int)ctrl->max_oob); |
| 1127 | tbytes = min_t(int, tbytes, ctrl->max_oob); |
| 1128 | |
| 1129 | for (j = 0; j < tbytes; j++) |
| 1130 | oob[j] = oob_reg_read(ctrl, j); |
| 1131 | return tbytes; |
| 1132 | } |
| 1133 | |
| 1134 | /* |
| 1135 | * write_oob_to_regs - write data to OOB registers |
| 1136 | * @i: sub-page sector index |
| 1137 | * @oob: buffer to write from |
| 1138 | * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) |
| 1139 | * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal |
| 1140 | */ |
| 1141 | static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, |
| 1142 | const u8 *oob, int sas, int sector_1k) |
| 1143 | { |
| 1144 | int tbytes = sas << sector_1k; |
| 1145 | int j; |
| 1146 | |
| 1147 | /* Adjust OOB values for 1K sector size */ |
| 1148 | if (sector_1k && (i & 0x01)) |
| 1149 | tbytes = max(0, tbytes - (int)ctrl->max_oob); |
| 1150 | tbytes = min_t(int, tbytes, ctrl->max_oob); |
| 1151 | |
| 1152 | for (j = 0; j < tbytes; j += 4) |
| 1153 | oob_reg_write(ctrl, j, |
| 1154 | (oob[j + 0] << 24) | |
| 1155 | (oob[j + 1] << 16) | |
| 1156 | (oob[j + 2] << 8) | |
| 1157 | (oob[j + 3] << 0)); |
| 1158 | return tbytes; |
| 1159 | } |
| 1160 | |
| 1161 | #ifndef __UBOOT__ |
| 1162 | static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data) |
| 1163 | { |
| 1164 | struct brcmnand_controller *ctrl = data; |
| 1165 | |
| 1166 | /* Discard all NAND_CTLRDY interrupts during DMA */ |
| 1167 | if (ctrl->dma_pending) |
| 1168 | return IRQ_HANDLED; |
| 1169 | |
| 1170 | complete(&ctrl->done); |
| 1171 | return IRQ_HANDLED; |
| 1172 | } |
| 1173 | |
| 1174 | /* Handle SoC-specific interrupt hardware */ |
| 1175 | static irqreturn_t brcmnand_irq(int irq, void *data) |
| 1176 | { |
| 1177 | struct brcmnand_controller *ctrl = data; |
| 1178 | |
| 1179 | if (ctrl->soc->ctlrdy_ack(ctrl->soc)) |
| 1180 | return brcmnand_ctlrdy_irq(irq, data); |
| 1181 | |
| 1182 | return IRQ_NONE; |
| 1183 | } |
| 1184 | |
| 1185 | static irqreturn_t brcmnand_dma_irq(int irq, void *data) |
| 1186 | { |
| 1187 | struct brcmnand_controller *ctrl = data; |
| 1188 | |
| 1189 | complete(&ctrl->dma_done); |
| 1190 | |
| 1191 | return IRQ_HANDLED; |
| 1192 | } |
| 1193 | #endif /* __UBOOT__ */ |
| 1194 | |
| 1195 | static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) |
| 1196 | { |
| 1197 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1198 | int ret; |
| 1199 | |
| 1200 | dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd, |
| 1201 | brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS)); |
| 1202 | BUG_ON(ctrl->cmd_pending != 0); |
| 1203 | ctrl->cmd_pending = cmd; |
| 1204 | |
| 1205 | ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); |
| 1206 | WARN_ON(ret); |
| 1207 | |
| 1208 | mb(); /* flush previous writes */ |
| 1209 | brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, |
| 1210 | cmd << brcmnand_cmd_shift(ctrl)); |
| 1211 | } |
| 1212 | |
| 1213 | /*********************************************************************** |
| 1214 | * NAND MTD API: read/program/erase |
| 1215 | ***********************************************************************/ |
| 1216 | |
| 1217 | static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat, |
| 1218 | unsigned int ctrl) |
| 1219 | { |
| 1220 | /* intentionally left blank */ |
| 1221 | } |
| 1222 | |
| 1223 | static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) |
| 1224 | { |
| 1225 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 1226 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1227 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1228 | |
| 1229 | #ifndef __UBOOT__ |
| 1230 | unsigned long timeo = msecs_to_jiffies(100); |
| 1231 | |
| 1232 | dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); |
| 1233 | if (ctrl->cmd_pending && |
| 1234 | wait_for_completion_timeout(&ctrl->done, timeo) <= 0) { |
| 1235 | u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) |
| 1236 | >> brcmnand_cmd_shift(ctrl); |
| 1237 | |
| 1238 | dev_err_ratelimited(ctrl->dev, |
| 1239 | "timeout waiting for command %#02x\n", cmd); |
| 1240 | dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", |
| 1241 | brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); |
| 1242 | } |
| 1243 | #else |
| 1244 | unsigned long timeo = 100; /* 100 msec */ |
| 1245 | int ret; |
| 1246 | |
| 1247 | dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); |
| 1248 | |
| 1249 | ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, timeo); |
| 1250 | WARN_ON(ret); |
| 1251 | #endif /* __UBOOT__ */ |
| 1252 | |
| 1253 | ctrl->cmd_pending = 0; |
| 1254 | return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & |
| 1255 | INTFC_FLASH_STATUS; |
| 1256 | } |
| 1257 | |
| 1258 | enum { |
| 1259 | LLOP_RE = BIT(16), |
| 1260 | LLOP_WE = BIT(17), |
| 1261 | LLOP_ALE = BIT(18), |
| 1262 | LLOP_CLE = BIT(19), |
| 1263 | LLOP_RETURN_IDLE = BIT(31), |
| 1264 | |
| 1265 | LLOP_DATA_MASK = GENMASK(15, 0), |
| 1266 | }; |
| 1267 | |
| 1268 | static int brcmnand_low_level_op(struct brcmnand_host *host, |
| 1269 | enum brcmnand_llop_type type, u32 data, |
| 1270 | bool last_op) |
| 1271 | { |
| 1272 | struct mtd_info *mtd = nand_to_mtd(&host->chip); |
| 1273 | struct nand_chip *chip = &host->chip; |
| 1274 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1275 | u32 tmp; |
| 1276 | |
| 1277 | tmp = data & LLOP_DATA_MASK; |
| 1278 | switch (type) { |
| 1279 | case LL_OP_CMD: |
| 1280 | tmp |= LLOP_WE | LLOP_CLE; |
| 1281 | break; |
| 1282 | case LL_OP_ADDR: |
| 1283 | /* WE | ALE */ |
| 1284 | tmp |= LLOP_WE | LLOP_ALE; |
| 1285 | break; |
| 1286 | case LL_OP_WR: |
| 1287 | /* WE */ |
| 1288 | tmp |= LLOP_WE; |
| 1289 | break; |
| 1290 | case LL_OP_RD: |
| 1291 | /* RE */ |
| 1292 | tmp |= LLOP_RE; |
| 1293 | break; |
| 1294 | } |
| 1295 | if (last_op) |
| 1296 | /* RETURN_IDLE */ |
| 1297 | tmp |= LLOP_RETURN_IDLE; |
| 1298 | |
| 1299 | dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); |
| 1300 | |
| 1301 | brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp); |
| 1302 | (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP); |
| 1303 | |
| 1304 | brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP); |
| 1305 | return brcmnand_waitfunc(mtd, chip); |
| 1306 | } |
| 1307 | |
| 1308 | static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command, |
| 1309 | int column, int page_addr) |
| 1310 | { |
| 1311 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 1312 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1313 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1314 | u64 addr = (u64)page_addr << chip->page_shift; |
| 1315 | int native_cmd = 0; |
| 1316 | |
| 1317 | if (command == NAND_CMD_READID || command == NAND_CMD_PARAM || |
| 1318 | command == NAND_CMD_RNDOUT) |
| 1319 | addr = (u64)column; |
| 1320 | /* Avoid propagating a negative, don't-care address */ |
| 1321 | else if (page_addr < 0) |
| 1322 | addr = 0; |
| 1323 | |
| 1324 | dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, |
| 1325 | (unsigned long long)addr); |
| 1326 | |
| 1327 | host->last_cmd = command; |
| 1328 | host->last_byte = 0; |
| 1329 | host->last_addr = addr; |
| 1330 | |
| 1331 | switch (command) { |
| 1332 | case NAND_CMD_RESET: |
| 1333 | native_cmd = CMD_FLASH_RESET; |
| 1334 | break; |
| 1335 | case NAND_CMD_STATUS: |
| 1336 | native_cmd = CMD_STATUS_READ; |
| 1337 | break; |
| 1338 | case NAND_CMD_READID: |
| 1339 | native_cmd = CMD_DEVICE_ID_READ; |
| 1340 | break; |
| 1341 | case NAND_CMD_READOOB: |
| 1342 | native_cmd = CMD_SPARE_AREA_READ; |
| 1343 | break; |
| 1344 | case NAND_CMD_ERASE1: |
| 1345 | native_cmd = CMD_BLOCK_ERASE; |
| 1346 | brcmnand_wp(mtd, 0); |
| 1347 | break; |
| 1348 | case NAND_CMD_PARAM: |
| 1349 | native_cmd = CMD_PARAMETER_READ; |
| 1350 | break; |
| 1351 | case NAND_CMD_SET_FEATURES: |
| 1352 | case NAND_CMD_GET_FEATURES: |
| 1353 | brcmnand_low_level_op(host, LL_OP_CMD, command, false); |
| 1354 | brcmnand_low_level_op(host, LL_OP_ADDR, column, false); |
| 1355 | break; |
| 1356 | case NAND_CMD_RNDOUT: |
| 1357 | native_cmd = CMD_PARAMETER_CHANGE_COL; |
| 1358 | addr &= ~((u64)(FC_BYTES - 1)); |
| 1359 | /* |
| 1360 | * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0 |
| 1361 | * NB: hwcfg.sector_size_1k may not be initialized yet |
| 1362 | */ |
| 1363 | if (brcmnand_get_sector_size_1k(host)) { |
| 1364 | host->hwcfg.sector_size_1k = |
| 1365 | brcmnand_get_sector_size_1k(host); |
| 1366 | brcmnand_set_sector_size_1k(host, 0); |
| 1367 | } |
| 1368 | break; |
| 1369 | } |
| 1370 | |
| 1371 | if (!native_cmd) |
| 1372 | return; |
| 1373 | |
| 1374 | brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, |
| 1375 | (host->cs << 16) | ((addr >> 32) & 0xffff)); |
| 1376 | (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); |
| 1377 | brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr)); |
| 1378 | (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); |
| 1379 | |
| 1380 | brcmnand_send_cmd(host, native_cmd); |
| 1381 | brcmnand_waitfunc(mtd, chip); |
| 1382 | |
| 1383 | if (native_cmd == CMD_PARAMETER_READ || |
| 1384 | native_cmd == CMD_PARAMETER_CHANGE_COL) { |
| 1385 | /* Copy flash cache word-wise */ |
| 1386 | u32 *flash_cache = (u32 *)ctrl->flash_cache; |
| 1387 | int i; |
| 1388 | |
| 1389 | brcmnand_soc_data_bus_prepare(ctrl->soc, true); |
| 1390 | |
| 1391 | /* |
| 1392 | * Must cache the FLASH_CACHE now, since changes in |
| 1393 | * SECTOR_SIZE_1K may invalidate it |
| 1394 | */ |
Philippe Reynes | 7f28cf6 | 2019-03-15 15:14:37 +0100 | [diff] [blame] | 1395 | for (i = 0; i < FC_WORDS; i++) { |
| 1396 | u32 fc; |
| 1397 | |
| 1398 | fc = brcmnand_read_fc(ctrl, i); |
| 1399 | |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1400 | /* |
| 1401 | * Flash cache is big endian for parameter pages, at |
| 1402 | * least on STB SoCs |
| 1403 | */ |
Philippe Reynes | 7f28cf6 | 2019-03-15 15:14:37 +0100 | [diff] [blame] | 1404 | if (ctrl->parameter_page_big_endian) |
| 1405 | flash_cache[i] = be32_to_cpu(fc); |
| 1406 | else |
| 1407 | flash_cache[i] = le32_to_cpu(fc); |
| 1408 | } |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 1409 | |
| 1410 | brcmnand_soc_data_bus_unprepare(ctrl->soc, true); |
| 1411 | |
| 1412 | /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */ |
| 1413 | if (host->hwcfg.sector_size_1k) |
| 1414 | brcmnand_set_sector_size_1k(host, |
| 1415 | host->hwcfg.sector_size_1k); |
| 1416 | } |
| 1417 | |
| 1418 | /* Re-enable protection is necessary only after erase */ |
| 1419 | if (command == NAND_CMD_ERASE1) |
| 1420 | brcmnand_wp(mtd, 1); |
| 1421 | } |
| 1422 | |
| 1423 | static uint8_t brcmnand_read_byte(struct mtd_info *mtd) |
| 1424 | { |
| 1425 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 1426 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1427 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1428 | uint8_t ret = 0; |
| 1429 | int addr, offs; |
| 1430 | |
| 1431 | switch (host->last_cmd) { |
| 1432 | case NAND_CMD_READID: |
| 1433 | if (host->last_byte < 4) |
| 1434 | ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >> |
| 1435 | (24 - (host->last_byte << 3)); |
| 1436 | else if (host->last_byte < 8) |
| 1437 | ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >> |
| 1438 | (56 - (host->last_byte << 3)); |
| 1439 | break; |
| 1440 | |
| 1441 | case NAND_CMD_READOOB: |
| 1442 | ret = oob_reg_read(ctrl, host->last_byte); |
| 1443 | break; |
| 1444 | |
| 1445 | case NAND_CMD_STATUS: |
| 1446 | ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & |
| 1447 | INTFC_FLASH_STATUS; |
| 1448 | if (wp_on) /* hide WP status */ |
| 1449 | ret |= NAND_STATUS_WP; |
| 1450 | break; |
| 1451 | |
| 1452 | case NAND_CMD_PARAM: |
| 1453 | case NAND_CMD_RNDOUT: |
| 1454 | addr = host->last_addr + host->last_byte; |
| 1455 | offs = addr & (FC_BYTES - 1); |
| 1456 | |
| 1457 | /* At FC_BYTES boundary, switch to next column */ |
| 1458 | if (host->last_byte > 0 && offs == 0) |
| 1459 | nand_change_read_column_op(chip, addr, NULL, 0, false); |
| 1460 | |
| 1461 | ret = ctrl->flash_cache[offs]; |
| 1462 | break; |
| 1463 | case NAND_CMD_GET_FEATURES: |
| 1464 | if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) { |
| 1465 | ret = 0; |
| 1466 | } else { |
| 1467 | bool last = host->last_byte == |
| 1468 | ONFI_SUBFEATURE_PARAM_LEN - 1; |
| 1469 | brcmnand_low_level_op(host, LL_OP_RD, 0, last); |
| 1470 | ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff; |
| 1471 | } |
| 1472 | } |
| 1473 | |
| 1474 | dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); |
| 1475 | host->last_byte++; |
| 1476 | |
| 1477 | return ret; |
| 1478 | } |
| 1479 | |
| 1480 | static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
| 1481 | { |
| 1482 | int i; |
| 1483 | |
| 1484 | for (i = 0; i < len; i++, buf++) |
| 1485 | *buf = brcmnand_read_byte(mtd); |
| 1486 | } |
| 1487 | |
| 1488 | static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf, |
| 1489 | int len) |
| 1490 | { |
| 1491 | int i; |
| 1492 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 1493 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1494 | |
| 1495 | switch (host->last_cmd) { |
| 1496 | case NAND_CMD_SET_FEATURES: |
| 1497 | for (i = 0; i < len; i++) |
| 1498 | brcmnand_low_level_op(host, LL_OP_WR, buf[i], |
| 1499 | (i + 1) == len); |
| 1500 | break; |
| 1501 | default: |
| 1502 | BUG(); |
| 1503 | break; |
| 1504 | } |
| 1505 | } |
| 1506 | |
| 1507 | /** |
| 1508 | * Construct a FLASH_DMA descriptor as part of a linked list. You must know the |
| 1509 | * following ahead of time: |
| 1510 | * - Is this descriptor the beginning or end of a linked list? |
| 1511 | * - What is the (DMA) address of the next descriptor in the linked list? |
| 1512 | */ |
| 1513 | #ifndef __UBOOT__ |
| 1514 | static int brcmnand_fill_dma_desc(struct brcmnand_host *host, |
| 1515 | struct brcm_nand_dma_desc *desc, u64 addr, |
| 1516 | dma_addr_t buf, u32 len, u8 dma_cmd, |
| 1517 | bool begin, bool end, |
| 1518 | dma_addr_t next_desc) |
| 1519 | { |
| 1520 | memset(desc, 0, sizeof(*desc)); |
| 1521 | /* Descriptors are written in native byte order (wordwise) */ |
| 1522 | desc->next_desc = lower_32_bits(next_desc); |
| 1523 | desc->next_desc_ext = upper_32_bits(next_desc); |
| 1524 | desc->cmd_irq = (dma_cmd << 24) | |
| 1525 | (end ? (0x03 << 8) : 0) | /* IRQ | STOP */ |
| 1526 | (!!begin) | ((!!end) << 1); /* head, tail */ |
| 1527 | #ifdef CONFIG_CPU_BIG_ENDIAN |
| 1528 | desc->cmd_irq |= 0x01 << 12; |
| 1529 | #endif |
| 1530 | desc->dram_addr = lower_32_bits(buf); |
| 1531 | desc->dram_addr_ext = upper_32_bits(buf); |
| 1532 | desc->tfr_len = len; |
| 1533 | desc->total_len = len; |
| 1534 | desc->flash_addr = lower_32_bits(addr); |
| 1535 | desc->flash_addr_ext = upper_32_bits(addr); |
| 1536 | desc->cs = host->cs; |
| 1537 | desc->status_valid = 0x01; |
| 1538 | return 0; |
| 1539 | } |
| 1540 | |
| 1541 | /** |
| 1542 | * Kick the FLASH_DMA engine, with a given DMA descriptor |
| 1543 | */ |
| 1544 | static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc) |
| 1545 | { |
| 1546 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1547 | unsigned long timeo = msecs_to_jiffies(100); |
| 1548 | |
| 1549 | flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); |
| 1550 | (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); |
| 1551 | flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc)); |
| 1552 | (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); |
| 1553 | |
| 1554 | /* Start FLASH_DMA engine */ |
| 1555 | ctrl->dma_pending = true; |
| 1556 | mb(); /* flush previous writes */ |
| 1557 | flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */ |
| 1558 | |
| 1559 | if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { |
| 1560 | dev_err(ctrl->dev, |
| 1561 | "timeout waiting for DMA; status %#x, error status %#x\n", |
| 1562 | flash_dma_readl(ctrl, FLASH_DMA_STATUS), |
| 1563 | flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS)); |
| 1564 | } |
| 1565 | ctrl->dma_pending = false; |
| 1566 | flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */ |
| 1567 | } |
| 1568 | |
| 1569 | static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf, |
| 1570 | u32 len, u8 dma_cmd) |
| 1571 | { |
| 1572 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1573 | dma_addr_t buf_pa; |
| 1574 | int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE; |
| 1575 | |
| 1576 | buf_pa = dma_map_single(ctrl->dev, buf, len, dir); |
| 1577 | if (dma_mapping_error(ctrl->dev, buf_pa)) { |
| 1578 | dev_err(ctrl->dev, "unable to map buffer for DMA\n"); |
| 1579 | return -ENOMEM; |
| 1580 | } |
| 1581 | |
| 1582 | brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, |
| 1583 | dma_cmd, true, true, 0); |
| 1584 | |
| 1585 | brcmnand_dma_run(host, ctrl->dma_pa); |
| 1586 | |
| 1587 | dma_unmap_single(ctrl->dev, buf_pa, len, dir); |
| 1588 | |
| 1589 | if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) |
| 1590 | return -EBADMSG; |
| 1591 | else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) |
| 1592 | return -EUCLEAN; |
| 1593 | |
| 1594 | return 0; |
| 1595 | } |
| 1596 | #endif /* __UBOOT__ */ |
| 1597 | |
| 1598 | /* |
| 1599 | * Assumes proper CS is already set |
| 1600 | */ |
| 1601 | static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, |
| 1602 | u64 addr, unsigned int trans, u32 *buf, |
| 1603 | u8 *oob, u64 *err_addr) |
| 1604 | { |
| 1605 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1606 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1607 | int i, j, ret = 0; |
| 1608 | |
| 1609 | /* Clear error addresses */ |
| 1610 | brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); |
| 1611 | brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); |
| 1612 | brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); |
| 1613 | brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); |
| 1614 | |
| 1615 | brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, |
| 1616 | (host->cs << 16) | ((addr >> 32) & 0xffff)); |
| 1617 | (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); |
| 1618 | |
| 1619 | for (i = 0; i < trans; i++, addr += FC_BYTES) { |
| 1620 | brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, |
| 1621 | lower_32_bits(addr)); |
| 1622 | (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); |
| 1623 | /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */ |
| 1624 | brcmnand_send_cmd(host, CMD_PAGE_READ); |
| 1625 | brcmnand_waitfunc(mtd, chip); |
| 1626 | |
| 1627 | if (likely(buf)) { |
| 1628 | brcmnand_soc_data_bus_prepare(ctrl->soc, false); |
| 1629 | |
| 1630 | for (j = 0; j < FC_WORDS; j++, buf++) |
| 1631 | *buf = brcmnand_read_fc(ctrl, j); |
| 1632 | |
| 1633 | brcmnand_soc_data_bus_unprepare(ctrl->soc, false); |
| 1634 | } |
| 1635 | |
| 1636 | if (oob) |
| 1637 | oob += read_oob_from_regs(ctrl, i, oob, |
| 1638 | mtd->oobsize / trans, |
| 1639 | host->hwcfg.sector_size_1k); |
| 1640 | |
| 1641 | if (!ret) { |
| 1642 | *err_addr = brcmnand_read_reg(ctrl, |
| 1643 | BRCMNAND_UNCORR_ADDR) | |
| 1644 | ((u64)(brcmnand_read_reg(ctrl, |
| 1645 | BRCMNAND_UNCORR_EXT_ADDR) |
| 1646 | & 0xffff) << 32); |
| 1647 | if (*err_addr) |
| 1648 | ret = -EBADMSG; |
| 1649 | } |
| 1650 | |
| 1651 | if (!ret) { |
| 1652 | *err_addr = brcmnand_read_reg(ctrl, |
| 1653 | BRCMNAND_CORR_ADDR) | |
| 1654 | ((u64)(brcmnand_read_reg(ctrl, |
| 1655 | BRCMNAND_CORR_EXT_ADDR) |
| 1656 | & 0xffff) << 32); |
| 1657 | if (*err_addr) |
| 1658 | ret = -EUCLEAN; |
| 1659 | } |
| 1660 | } |
| 1661 | |
| 1662 | return ret; |
| 1663 | } |
| 1664 | |
| 1665 | /* |
| 1666 | * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC |
| 1667 | * error |
| 1668 | * |
| 1669 | * Because the HW ECC signals an ECC error if an erase paged has even a single |
| 1670 | * bitflip, we must check each ECC error to see if it is actually an erased |
| 1671 | * page with bitflips, not a truly corrupted page. |
| 1672 | * |
| 1673 | * On a real error, return a negative error code (-EBADMSG for ECC error), and |
| 1674 | * buf will contain raw data. |
| 1675 | * Otherwise, buf gets filled with 0xffs and return the maximum number of |
| 1676 | * bitflips-per-ECC-sector to the caller. |
| 1677 | * |
| 1678 | */ |
| 1679 | static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd, |
| 1680 | struct nand_chip *chip, void *buf, u64 addr) |
| 1681 | { |
| 1682 | int i, sas; |
| 1683 | void *oob = chip->oob_poi; |
| 1684 | int bitflips = 0; |
| 1685 | int page = addr >> chip->page_shift; |
| 1686 | int ret; |
| 1687 | |
| 1688 | if (!buf) { |
| 1689 | #ifndef __UBOOT__ |
| 1690 | buf = chip->data_buf; |
| 1691 | #else |
| 1692 | buf = chip->buffers->databuf; |
| 1693 | #endif |
| 1694 | /* Invalidate page cache */ |
| 1695 | chip->pagebuf = -1; |
| 1696 | } |
| 1697 | |
| 1698 | sas = mtd->oobsize / chip->ecc.steps; |
| 1699 | |
| 1700 | /* read without ecc for verification */ |
| 1701 | ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page); |
| 1702 | if (ret) |
| 1703 | return ret; |
| 1704 | |
| 1705 | for (i = 0; i < chip->ecc.steps; i++, oob += sas) { |
| 1706 | ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size, |
| 1707 | oob, sas, NULL, 0, |
| 1708 | chip->ecc.strength); |
| 1709 | if (ret < 0) |
| 1710 | return ret; |
| 1711 | |
| 1712 | bitflips = max(bitflips, ret); |
| 1713 | } |
| 1714 | |
| 1715 | return bitflips; |
| 1716 | } |
| 1717 | |
| 1718 | static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip, |
| 1719 | u64 addr, unsigned int trans, u32 *buf, u8 *oob) |
| 1720 | { |
| 1721 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1722 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1723 | u64 err_addr = 0; |
| 1724 | int err; |
| 1725 | bool retry = true; |
| 1726 | |
| 1727 | dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); |
| 1728 | |
| 1729 | try_dmaread: |
| 1730 | brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0); |
| 1731 | |
| 1732 | #ifndef __UBOOT__ |
| 1733 | if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { |
| 1734 | err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES, |
| 1735 | CMD_PAGE_READ); |
| 1736 | if (err) { |
| 1737 | if (mtd_is_bitflip_or_eccerr(err)) |
| 1738 | err_addr = addr; |
| 1739 | else |
| 1740 | return -EIO; |
| 1741 | } |
| 1742 | } else { |
| 1743 | if (oob) |
| 1744 | memset(oob, 0x99, mtd->oobsize); |
| 1745 | |
| 1746 | err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, |
| 1747 | oob, &err_addr); |
| 1748 | } |
| 1749 | #else |
| 1750 | if (oob) |
| 1751 | memset(oob, 0x99, mtd->oobsize); |
| 1752 | |
| 1753 | err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, |
| 1754 | oob, &err_addr); |
| 1755 | #endif /* __UBOOT__ */ |
| 1756 | |
| 1757 | if (mtd_is_eccerr(err)) { |
| 1758 | /* |
| 1759 | * On controller version and 7.0, 7.1 , DMA read after a |
| 1760 | * prior PIO read that reported uncorrectable error, |
| 1761 | * the DMA engine captures this error following DMA read |
| 1762 | * cleared only on subsequent DMA read, so just retry once |
| 1763 | * to clear a possible false error reported for current DMA |
| 1764 | * read |
| 1765 | */ |
| 1766 | if ((ctrl->nand_version == 0x0700) || |
| 1767 | (ctrl->nand_version == 0x0701)) { |
| 1768 | if (retry) { |
| 1769 | retry = false; |
| 1770 | goto try_dmaread; |
| 1771 | } |
| 1772 | } |
| 1773 | |
| 1774 | /* |
| 1775 | * Controller version 7.2 has hw encoder to detect erased page |
| 1776 | * bitflips, apply sw verification for older controllers only |
| 1777 | */ |
| 1778 | if (ctrl->nand_version < 0x0702) { |
| 1779 | err = brcmstb_nand_verify_erased_page(mtd, chip, buf, |
| 1780 | addr); |
| 1781 | /* erased page bitflips corrected */ |
| 1782 | if (err >= 0) |
| 1783 | return err; |
| 1784 | } |
| 1785 | |
| 1786 | dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", |
| 1787 | (unsigned long long)err_addr); |
| 1788 | mtd->ecc_stats.failed++; |
| 1789 | /* NAND layer expects zero on ECC errors */ |
| 1790 | return 0; |
| 1791 | } |
| 1792 | |
| 1793 | if (mtd_is_bitflip(err)) { |
| 1794 | unsigned int corrected = brcmnand_count_corrected(ctrl); |
| 1795 | |
| 1796 | dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", |
| 1797 | (unsigned long long)err_addr); |
| 1798 | mtd->ecc_stats.corrected += corrected; |
| 1799 | /* Always exceed the software-imposed threshold */ |
| 1800 | return max(mtd->bitflip_threshold, corrected); |
| 1801 | } |
| 1802 | |
| 1803 | return 0; |
| 1804 | } |
| 1805 | |
| 1806 | static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip, |
| 1807 | uint8_t *buf, int oob_required, int page) |
| 1808 | { |
| 1809 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1810 | u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; |
| 1811 | |
| 1812 | nand_read_page_op(chip, page, 0, NULL, 0); |
| 1813 | |
| 1814 | return brcmnand_read(mtd, chip, host->last_addr, |
| 1815 | mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); |
| 1816 | } |
| 1817 | |
| 1818 | static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
| 1819 | uint8_t *buf, int oob_required, int page) |
| 1820 | { |
| 1821 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1822 | u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; |
| 1823 | int ret; |
| 1824 | |
| 1825 | nand_read_page_op(chip, page, 0, NULL, 0); |
| 1826 | |
| 1827 | brcmnand_set_ecc_enabled(host, 0); |
| 1828 | ret = brcmnand_read(mtd, chip, host->last_addr, |
| 1829 | mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); |
| 1830 | brcmnand_set_ecc_enabled(host, 1); |
| 1831 | return ret; |
| 1832 | } |
| 1833 | |
| 1834 | static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
| 1835 | int page) |
| 1836 | { |
| 1837 | return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, |
| 1838 | mtd->writesize >> FC_SHIFT, |
| 1839 | NULL, (u8 *)chip->oob_poi); |
| 1840 | } |
| 1841 | |
| 1842 | static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, |
| 1843 | int page) |
| 1844 | { |
| 1845 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1846 | |
| 1847 | brcmnand_set_ecc_enabled(host, 0); |
| 1848 | brcmnand_read(mtd, chip, (u64)page << chip->page_shift, |
| 1849 | mtd->writesize >> FC_SHIFT, |
| 1850 | NULL, (u8 *)chip->oob_poi); |
| 1851 | brcmnand_set_ecc_enabled(host, 1); |
| 1852 | return 0; |
| 1853 | } |
| 1854 | |
| 1855 | static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip, |
| 1856 | u64 addr, const u32 *buf, u8 *oob) |
| 1857 | { |
| 1858 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1859 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1860 | unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; |
| 1861 | int status, ret = 0; |
| 1862 | |
| 1863 | dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); |
| 1864 | |
| 1865 | if (unlikely((unsigned long)buf & 0x03)) { |
| 1866 | dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); |
| 1867 | buf = (u32 *)((unsigned long)buf & ~0x03); |
| 1868 | } |
| 1869 | |
| 1870 | brcmnand_wp(mtd, 0); |
| 1871 | |
| 1872 | for (i = 0; i < ctrl->max_oob; i += 4) |
| 1873 | oob_reg_write(ctrl, i, 0xffffffff); |
| 1874 | |
| 1875 | #ifndef __UBOOT__ |
| 1876 | if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { |
| 1877 | if (brcmnand_dma_trans(host, addr, (u32 *)buf, |
| 1878 | mtd->writesize, CMD_PROGRAM_PAGE)) |
| 1879 | ret = -EIO; |
| 1880 | goto out; |
| 1881 | } |
| 1882 | #endif /* __UBOOT__ */ |
| 1883 | |
| 1884 | brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, |
| 1885 | (host->cs << 16) | ((addr >> 32) & 0xffff)); |
| 1886 | (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); |
| 1887 | |
| 1888 | for (i = 0; i < trans; i++, addr += FC_BYTES) { |
| 1889 | /* full address MUST be set before populating FC */ |
| 1890 | brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, |
| 1891 | lower_32_bits(addr)); |
| 1892 | (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); |
| 1893 | |
| 1894 | if (buf) { |
| 1895 | brcmnand_soc_data_bus_prepare(ctrl->soc, false); |
| 1896 | |
| 1897 | for (j = 0; j < FC_WORDS; j++, buf++) |
| 1898 | brcmnand_write_fc(ctrl, j, *buf); |
| 1899 | |
| 1900 | brcmnand_soc_data_bus_unprepare(ctrl->soc, false); |
| 1901 | } else if (oob) { |
| 1902 | for (j = 0; j < FC_WORDS; j++) |
| 1903 | brcmnand_write_fc(ctrl, j, 0xffffffff); |
| 1904 | } |
| 1905 | |
| 1906 | if (oob) { |
| 1907 | oob += write_oob_to_regs(ctrl, i, oob, |
| 1908 | mtd->oobsize / trans, |
| 1909 | host->hwcfg.sector_size_1k); |
| 1910 | } |
| 1911 | |
| 1912 | /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */ |
| 1913 | brcmnand_send_cmd(host, CMD_PROGRAM_PAGE); |
| 1914 | status = brcmnand_waitfunc(mtd, chip); |
| 1915 | |
| 1916 | if (status & NAND_STATUS_FAIL) { |
| 1917 | dev_info(ctrl->dev, "program failed at %llx\n", |
| 1918 | (unsigned long long)addr); |
| 1919 | ret = -EIO; |
| 1920 | goto out; |
| 1921 | } |
| 1922 | } |
| 1923 | out: |
| 1924 | brcmnand_wp(mtd, 1); |
| 1925 | return ret; |
| 1926 | } |
| 1927 | |
| 1928 | static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
| 1929 | const uint8_t *buf, int oob_required, int page) |
| 1930 | { |
| 1931 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1932 | void *oob = oob_required ? chip->oob_poi : NULL; |
| 1933 | |
| 1934 | nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
| 1935 | brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); |
| 1936 | |
| 1937 | return nand_prog_page_end_op(chip); |
| 1938 | } |
| 1939 | |
| 1940 | static int brcmnand_write_page_raw(struct mtd_info *mtd, |
| 1941 | struct nand_chip *chip, const uint8_t *buf, |
| 1942 | int oob_required, int page) |
| 1943 | { |
| 1944 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1945 | void *oob = oob_required ? chip->oob_poi : NULL; |
| 1946 | |
| 1947 | nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
| 1948 | brcmnand_set_ecc_enabled(host, 0); |
| 1949 | brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); |
| 1950 | brcmnand_set_ecc_enabled(host, 1); |
| 1951 | |
| 1952 | return nand_prog_page_end_op(chip); |
| 1953 | } |
| 1954 | |
| 1955 | static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
| 1956 | int page) |
| 1957 | { |
| 1958 | return brcmnand_write(mtd, chip, (u64)page << chip->page_shift, |
| 1959 | NULL, chip->oob_poi); |
| 1960 | } |
| 1961 | |
| 1962 | static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, |
| 1963 | int page) |
| 1964 | { |
| 1965 | struct brcmnand_host *host = nand_get_controller_data(chip); |
| 1966 | int ret; |
| 1967 | |
| 1968 | brcmnand_set_ecc_enabled(host, 0); |
| 1969 | ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, |
| 1970 | (u8 *)chip->oob_poi); |
| 1971 | brcmnand_set_ecc_enabled(host, 1); |
| 1972 | |
| 1973 | return ret; |
| 1974 | } |
| 1975 | |
| 1976 | /*********************************************************************** |
| 1977 | * Per-CS setup (1 NAND device) |
| 1978 | ***********************************************************************/ |
| 1979 | |
| 1980 | static int brcmnand_set_cfg(struct brcmnand_host *host, |
| 1981 | struct brcmnand_cfg *cfg) |
| 1982 | { |
| 1983 | struct brcmnand_controller *ctrl = host->ctrl; |
| 1984 | struct nand_chip *chip = &host->chip; |
| 1985 | u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); |
| 1986 | u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, |
| 1987 | BRCMNAND_CS_CFG_EXT); |
| 1988 | u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, |
| 1989 | BRCMNAND_CS_ACC_CONTROL); |
| 1990 | u8 block_size = 0, page_size = 0, device_size = 0; |
| 1991 | u32 tmp; |
| 1992 | |
| 1993 | if (ctrl->block_sizes) { |
| 1994 | int i, found; |
| 1995 | |
| 1996 | for (i = 0, found = 0; ctrl->block_sizes[i]; i++) |
| 1997 | if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { |
| 1998 | block_size = i; |
| 1999 | found = 1; |
| 2000 | } |
| 2001 | if (!found) { |
| 2002 | dev_warn(ctrl->dev, "invalid block size %u\n", |
| 2003 | cfg->block_size); |
| 2004 | return -EINVAL; |
| 2005 | } |
| 2006 | } else { |
| 2007 | block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); |
| 2008 | } |
| 2009 | |
| 2010 | if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && |
| 2011 | cfg->block_size > ctrl->max_block_size)) { |
| 2012 | dev_warn(ctrl->dev, "invalid block size %u\n", |
| 2013 | cfg->block_size); |
| 2014 | block_size = 0; |
| 2015 | } |
| 2016 | |
| 2017 | if (ctrl->page_sizes) { |
| 2018 | int i, found; |
| 2019 | |
| 2020 | for (i = 0, found = 0; ctrl->page_sizes[i]; i++) |
| 2021 | if (ctrl->page_sizes[i] == cfg->page_size) { |
| 2022 | page_size = i; |
| 2023 | found = 1; |
| 2024 | } |
| 2025 | if (!found) { |
| 2026 | dev_warn(ctrl->dev, "invalid page size %u\n", |
| 2027 | cfg->page_size); |
| 2028 | return -EINVAL; |
| 2029 | } |
| 2030 | } else { |
| 2031 | page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); |
| 2032 | } |
| 2033 | |
| 2034 | if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && |
| 2035 | cfg->page_size > ctrl->max_page_size)) { |
| 2036 | dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); |
| 2037 | return -EINVAL; |
| 2038 | } |
| 2039 | |
| 2040 | if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { |
| 2041 | dev_warn(ctrl->dev, "invalid device size 0x%llx\n", |
| 2042 | (unsigned long long)cfg->device_size); |
| 2043 | return -EINVAL; |
| 2044 | } |
| 2045 | device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); |
| 2046 | |
| 2047 | tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | |
| 2048 | (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | |
| 2049 | (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | |
| 2050 | (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | |
| 2051 | (device_size << CFG_DEVICE_SIZE_SHIFT); |
| 2052 | if (cfg_offs == cfg_ext_offs) { |
| 2053 | tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) | |
| 2054 | (block_size << CFG_BLK_SIZE_SHIFT); |
| 2055 | nand_writereg(ctrl, cfg_offs, tmp); |
| 2056 | } else { |
| 2057 | nand_writereg(ctrl, cfg_offs, tmp); |
| 2058 | tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) | |
| 2059 | (block_size << CFG_EXT_BLK_SIZE_SHIFT); |
| 2060 | nand_writereg(ctrl, cfg_ext_offs, tmp); |
| 2061 | } |
| 2062 | |
| 2063 | tmp = nand_readreg(ctrl, acc_control_offs); |
| 2064 | tmp &= ~brcmnand_ecc_level_mask(ctrl); |
| 2065 | tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; |
| 2066 | tmp &= ~brcmnand_spare_area_mask(ctrl); |
| 2067 | tmp |= cfg->spare_area_size; |
| 2068 | nand_writereg(ctrl, acc_control_offs, tmp); |
| 2069 | |
| 2070 | brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); |
| 2071 | |
| 2072 | /* threshold = ceil(BCH-level * 0.75) */ |
| 2073 | brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); |
| 2074 | |
| 2075 | return 0; |
| 2076 | } |
| 2077 | |
| 2078 | static void brcmnand_print_cfg(struct brcmnand_host *host, |
| 2079 | char *buf, struct brcmnand_cfg *cfg) |
| 2080 | { |
| 2081 | buf += sprintf(buf, |
| 2082 | "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", |
| 2083 | (unsigned long long)cfg->device_size >> 20, |
| 2084 | cfg->block_size >> 10, |
| 2085 | cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, |
| 2086 | cfg->page_size >= 1024 ? "KiB" : "B", |
| 2087 | cfg->spare_area_size, cfg->device_width); |
| 2088 | |
| 2089 | /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */ |
| 2090 | if (is_hamming_ecc(host->ctrl, cfg)) |
| 2091 | sprintf(buf, ", Hamming ECC"); |
| 2092 | else if (cfg->sector_size_1k) |
| 2093 | sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); |
| 2094 | else |
| 2095 | sprintf(buf, ", BCH-%u", cfg->ecc_level); |
| 2096 | } |
| 2097 | |
| 2098 | /* |
| 2099 | * Minimum number of bytes to address a page. Calculated as: |
| 2100 | * roundup(log2(size / page-size) / 8) |
| 2101 | * |
| 2102 | * NB: the following does not "round up" for non-power-of-2 'size'; but this is |
| 2103 | * OK because many other things will break if 'size' is irregular... |
| 2104 | */ |
| 2105 | static inline int get_blk_adr_bytes(u64 size, u32 writesize) |
| 2106 | { |
| 2107 | return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; |
| 2108 | } |
| 2109 | |
| 2110 | static int brcmnand_setup_dev(struct brcmnand_host *host) |
| 2111 | { |
| 2112 | struct mtd_info *mtd = nand_to_mtd(&host->chip); |
| 2113 | struct nand_chip *chip = &host->chip; |
| 2114 | struct brcmnand_controller *ctrl = host->ctrl; |
| 2115 | struct brcmnand_cfg *cfg = &host->hwcfg; |
| 2116 | char msg[128]; |
| 2117 | u32 offs, tmp, oob_sector; |
| 2118 | int ret; |
| 2119 | |
| 2120 | memset(cfg, 0, sizeof(*cfg)); |
| 2121 | |
| 2122 | #ifndef __UBOOT__ |
| 2123 | ret = of_property_read_u32(nand_get_flash_node(chip), |
| 2124 | "brcm,nand-oob-sector-size", |
| 2125 | &oob_sector); |
| 2126 | #else |
| 2127 | ret = ofnode_read_u32(nand_get_flash_node(chip), |
| 2128 | "brcm,nand-oob-sector-size", |
| 2129 | &oob_sector); |
| 2130 | #endif /* __UBOOT__ */ |
| 2131 | if (ret) { |
| 2132 | /* Use detected size */ |
| 2133 | cfg->spare_area_size = mtd->oobsize / |
| 2134 | (mtd->writesize >> FC_SHIFT); |
| 2135 | } else { |
| 2136 | cfg->spare_area_size = oob_sector; |
| 2137 | } |
| 2138 | if (cfg->spare_area_size > ctrl->max_oob) |
| 2139 | cfg->spare_area_size = ctrl->max_oob; |
| 2140 | /* |
| 2141 | * Set oobsize to be consistent with controller's spare_area_size, as |
| 2142 | * the rest is inaccessible. |
| 2143 | */ |
| 2144 | mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); |
| 2145 | |
| 2146 | cfg->device_size = mtd->size; |
| 2147 | cfg->block_size = mtd->erasesize; |
| 2148 | cfg->page_size = mtd->writesize; |
| 2149 | cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; |
| 2150 | cfg->col_adr_bytes = 2; |
| 2151 | cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); |
| 2152 | |
| 2153 | if (chip->ecc.mode != NAND_ECC_HW) { |
| 2154 | dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", |
| 2155 | chip->ecc.mode); |
| 2156 | return -EINVAL; |
| 2157 | } |
| 2158 | |
| 2159 | if (chip->ecc.algo == NAND_ECC_UNKNOWN) { |
| 2160 | if (chip->ecc.strength == 1 && chip->ecc.size == 512) |
| 2161 | /* Default to Hamming for 1-bit ECC, if unspecified */ |
| 2162 | chip->ecc.algo = NAND_ECC_HAMMING; |
| 2163 | else |
| 2164 | /* Otherwise, BCH */ |
| 2165 | chip->ecc.algo = NAND_ECC_BCH; |
| 2166 | } |
| 2167 | |
| 2168 | if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 || |
| 2169 | chip->ecc.size != 512)) { |
| 2170 | dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", |
| 2171 | chip->ecc.strength, chip->ecc.size); |
| 2172 | return -EINVAL; |
| 2173 | } |
| 2174 | |
| 2175 | switch (chip->ecc.size) { |
| 2176 | case 512: |
| 2177 | if (chip->ecc.algo == NAND_ECC_HAMMING) |
| 2178 | cfg->ecc_level = 15; |
| 2179 | else |
| 2180 | cfg->ecc_level = chip->ecc.strength; |
| 2181 | cfg->sector_size_1k = 0; |
| 2182 | break; |
| 2183 | case 1024: |
| 2184 | if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { |
| 2185 | dev_err(ctrl->dev, "1KB sectors not supported\n"); |
| 2186 | return -EINVAL; |
| 2187 | } |
| 2188 | if (chip->ecc.strength & 0x1) { |
| 2189 | dev_err(ctrl->dev, |
| 2190 | "odd ECC not supported with 1KB sectors\n"); |
| 2191 | return -EINVAL; |
| 2192 | } |
| 2193 | |
| 2194 | cfg->ecc_level = chip->ecc.strength >> 1; |
| 2195 | cfg->sector_size_1k = 1; |
| 2196 | break; |
| 2197 | default: |
| 2198 | dev_err(ctrl->dev, "unsupported ECC size: %d\n", |
| 2199 | chip->ecc.size); |
| 2200 | return -EINVAL; |
| 2201 | } |
| 2202 | |
| 2203 | cfg->ful_adr_bytes = cfg->blk_adr_bytes; |
| 2204 | if (mtd->writesize > 512) |
| 2205 | cfg->ful_adr_bytes += cfg->col_adr_bytes; |
| 2206 | else |
| 2207 | cfg->ful_adr_bytes += 1; |
| 2208 | |
| 2209 | ret = brcmnand_set_cfg(host, cfg); |
| 2210 | if (ret) |
| 2211 | return ret; |
| 2212 | |
| 2213 | brcmnand_set_ecc_enabled(host, 1); |
| 2214 | |
| 2215 | brcmnand_print_cfg(host, msg, cfg); |
| 2216 | dev_info(ctrl->dev, "detected %s\n", msg); |
| 2217 | |
| 2218 | /* Configure ACC_CONTROL */ |
| 2219 | offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); |
| 2220 | tmp = nand_readreg(ctrl, offs); |
| 2221 | tmp &= ~ACC_CONTROL_PARTIAL_PAGE; |
| 2222 | tmp &= ~ACC_CONTROL_RD_ERASED; |
| 2223 | |
| 2224 | /* We need to turn on Read from erased paged protected by ECC */ |
| 2225 | if (ctrl->nand_version >= 0x0702) |
| 2226 | tmp |= ACC_CONTROL_RD_ERASED; |
| 2227 | tmp &= ~ACC_CONTROL_FAST_PGM_RDIN; |
| 2228 | if (ctrl->features & BRCMNAND_HAS_PREFETCH) |
| 2229 | tmp &= ~ACC_CONTROL_PREFETCH; |
| 2230 | |
| 2231 | nand_writereg(ctrl, offs, tmp); |
| 2232 | |
| 2233 | return 0; |
| 2234 | } |
| 2235 | |
| 2236 | #ifndef __UBOOT__ |
| 2237 | static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn) |
| 2238 | #else |
| 2239 | static int brcmnand_init_cs(struct brcmnand_host *host, ofnode dn) |
| 2240 | #endif |
| 2241 | { |
| 2242 | struct brcmnand_controller *ctrl = host->ctrl; |
| 2243 | #ifndef __UBOOT__ |
| 2244 | struct platform_device *pdev = host->pdev; |
| 2245 | #else |
| 2246 | struct udevice *pdev = host->pdev; |
| 2247 | #endif /* __UBOOT__ */ |
| 2248 | struct mtd_info *mtd; |
| 2249 | struct nand_chip *chip; |
| 2250 | int ret; |
| 2251 | u16 cfg_offs; |
| 2252 | |
| 2253 | #ifndef __UBOOT__ |
| 2254 | ret = of_property_read_u32(dn, "reg", &host->cs); |
| 2255 | #else |
| 2256 | ret = ofnode_read_s32(dn, "reg", &host->cs); |
| 2257 | #endif |
| 2258 | if (ret) { |
| 2259 | dev_err(&pdev->dev, "can't get chip-select\n"); |
| 2260 | return -ENXIO; |
| 2261 | } |
| 2262 | |
| 2263 | mtd = nand_to_mtd(&host->chip); |
| 2264 | chip = &host->chip; |
| 2265 | |
| 2266 | nand_set_flash_node(chip, dn); |
| 2267 | nand_set_controller_data(chip, host); |
| 2268 | #ifndef __UBOOT__ |
| 2269 | mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d", |
| 2270 | host->cs); |
| 2271 | #else |
| 2272 | mtd->name = devm_kasprintf(pdev, GFP_KERNEL, "brcmnand.%d", |
| 2273 | host->cs); |
| 2274 | #endif /* __UBOOT__ */ |
| 2275 | if (!mtd->name) |
| 2276 | return -ENOMEM; |
| 2277 | |
| 2278 | mtd->owner = THIS_MODULE; |
| 2279 | #ifndef __UBOOT__ |
| 2280 | mtd->dev.parent = &pdev->dev; |
| 2281 | #else |
| 2282 | mtd->dev->parent = pdev; |
| 2283 | #endif /* __UBOOT__ */ |
| 2284 | |
| 2285 | chip->IO_ADDR_R = (void __iomem *)0xdeadbeef; |
| 2286 | chip->IO_ADDR_W = (void __iomem *)0xdeadbeef; |
| 2287 | |
| 2288 | chip->cmd_ctrl = brcmnand_cmd_ctrl; |
| 2289 | chip->cmdfunc = brcmnand_cmdfunc; |
| 2290 | chip->waitfunc = brcmnand_waitfunc; |
| 2291 | chip->read_byte = brcmnand_read_byte; |
| 2292 | chip->read_buf = brcmnand_read_buf; |
| 2293 | chip->write_buf = brcmnand_write_buf; |
| 2294 | |
| 2295 | chip->ecc.mode = NAND_ECC_HW; |
| 2296 | chip->ecc.read_page = brcmnand_read_page; |
| 2297 | chip->ecc.write_page = brcmnand_write_page; |
| 2298 | chip->ecc.read_page_raw = brcmnand_read_page_raw; |
| 2299 | chip->ecc.write_page_raw = brcmnand_write_page_raw; |
| 2300 | chip->ecc.write_oob_raw = brcmnand_write_oob_raw; |
| 2301 | chip->ecc.read_oob_raw = brcmnand_read_oob_raw; |
| 2302 | chip->ecc.read_oob = brcmnand_read_oob; |
| 2303 | chip->ecc.write_oob = brcmnand_write_oob; |
| 2304 | |
| 2305 | chip->controller = &ctrl->controller; |
| 2306 | |
| 2307 | /* |
| 2308 | * The bootloader might have configured 16bit mode but |
| 2309 | * NAND READID command only works in 8bit mode. We force |
| 2310 | * 8bit mode here to ensure that NAND READID commands works. |
| 2311 | */ |
| 2312 | cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); |
| 2313 | nand_writereg(ctrl, cfg_offs, |
| 2314 | nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH); |
| 2315 | |
| 2316 | ret = nand_scan_ident(mtd, 1, NULL); |
| 2317 | if (ret) |
| 2318 | return ret; |
| 2319 | |
| 2320 | chip->options |= NAND_NO_SUBPAGE_WRITE; |
| 2321 | /* |
| 2322 | * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA |
| 2323 | * to/from, and have nand_base pass us a bounce buffer instead, as |
| 2324 | * needed. |
| 2325 | */ |
| 2326 | chip->options |= NAND_USE_BOUNCE_BUFFER; |
| 2327 | |
| 2328 | if (chip->bbt_options & NAND_BBT_USE_FLASH) |
| 2329 | chip->bbt_options |= NAND_BBT_NO_OOB; |
| 2330 | |
| 2331 | if (brcmnand_setup_dev(host)) |
| 2332 | return -ENXIO; |
| 2333 | |
| 2334 | chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; |
| 2335 | /* only use our internal HW threshold */ |
| 2336 | mtd->bitflip_threshold = 1; |
| 2337 | |
William Zhang | 1100e49 | 2019-09-04 10:51:13 -0700 | [diff] [blame] | 2338 | chip->ecc.layout = brcmstb_choose_ecc_layout(host); |
| 2339 | if (!chip->ecc.layout) |
| 2340 | return -ENXIO; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 2341 | |
| 2342 | ret = nand_scan_tail(mtd); |
| 2343 | if (ret) |
| 2344 | return ret; |
| 2345 | |
| 2346 | #ifndef __UBOOT__ |
| 2347 | ret = mtd_device_register(mtd, NULL, 0); |
| 2348 | if (ret) |
| 2349 | nand_cleanup(chip); |
| 2350 | #else |
| 2351 | ret = nand_register(0, mtd); |
| 2352 | #endif /* __UBOOT__ */ |
| 2353 | |
| 2354 | return ret; |
| 2355 | } |
| 2356 | |
| 2357 | #ifndef __UBOOT__ |
| 2358 | static void brcmnand_save_restore_cs_config(struct brcmnand_host *host, |
| 2359 | int restore) |
| 2360 | { |
| 2361 | struct brcmnand_controller *ctrl = host->ctrl; |
| 2362 | u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); |
| 2363 | u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, |
| 2364 | BRCMNAND_CS_CFG_EXT); |
| 2365 | u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, |
| 2366 | BRCMNAND_CS_ACC_CONTROL); |
| 2367 | u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); |
| 2368 | u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); |
| 2369 | |
| 2370 | if (restore) { |
| 2371 | nand_writereg(ctrl, cfg_offs, host->hwcfg.config); |
| 2372 | if (cfg_offs != cfg_ext_offs) |
| 2373 | nand_writereg(ctrl, cfg_ext_offs, |
| 2374 | host->hwcfg.config_ext); |
| 2375 | nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); |
| 2376 | nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); |
| 2377 | nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); |
| 2378 | } else { |
| 2379 | host->hwcfg.config = nand_readreg(ctrl, cfg_offs); |
| 2380 | if (cfg_offs != cfg_ext_offs) |
| 2381 | host->hwcfg.config_ext = |
| 2382 | nand_readreg(ctrl, cfg_ext_offs); |
| 2383 | host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); |
| 2384 | host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); |
| 2385 | host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); |
| 2386 | } |
| 2387 | } |
| 2388 | |
| 2389 | static int brcmnand_suspend(struct device *dev) |
| 2390 | { |
| 2391 | struct brcmnand_controller *ctrl = dev_get_drvdata(dev); |
| 2392 | struct brcmnand_host *host; |
| 2393 | |
| 2394 | list_for_each_entry(host, &ctrl->host_list, node) |
| 2395 | brcmnand_save_restore_cs_config(host, 0); |
| 2396 | |
| 2397 | ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); |
| 2398 | ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); |
| 2399 | ctrl->corr_stat_threshold = |
| 2400 | brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD); |
| 2401 | |
| 2402 | if (has_flash_dma(ctrl)) |
| 2403 | ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); |
| 2404 | |
| 2405 | return 0; |
| 2406 | } |
| 2407 | |
| 2408 | static int brcmnand_resume(struct device *dev) |
| 2409 | { |
| 2410 | struct brcmnand_controller *ctrl = dev_get_drvdata(dev); |
| 2411 | struct brcmnand_host *host; |
| 2412 | |
| 2413 | if (has_flash_dma(ctrl)) { |
| 2414 | flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); |
| 2415 | flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); |
| 2416 | } |
| 2417 | |
| 2418 | brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); |
| 2419 | brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); |
| 2420 | brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD, |
| 2421 | ctrl->corr_stat_threshold); |
| 2422 | if (ctrl->soc) { |
| 2423 | /* Clear/re-enable interrupt */ |
| 2424 | ctrl->soc->ctlrdy_ack(ctrl->soc); |
| 2425 | ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); |
| 2426 | } |
| 2427 | |
| 2428 | list_for_each_entry(host, &ctrl->host_list, node) { |
| 2429 | struct nand_chip *chip = &host->chip; |
| 2430 | |
| 2431 | brcmnand_save_restore_cs_config(host, 1); |
| 2432 | |
| 2433 | /* Reset the chip, required by some chips after power-up */ |
| 2434 | nand_reset_op(chip); |
| 2435 | } |
| 2436 | |
| 2437 | return 0; |
| 2438 | } |
| 2439 | |
| 2440 | const struct dev_pm_ops brcmnand_pm_ops = { |
| 2441 | .suspend = brcmnand_suspend, |
| 2442 | .resume = brcmnand_resume, |
| 2443 | }; |
| 2444 | EXPORT_SYMBOL_GPL(brcmnand_pm_ops); |
| 2445 | |
| 2446 | static const struct of_device_id brcmnand_of_match[] = { |
| 2447 | { .compatible = "brcm,brcmnand-v4.0" }, |
| 2448 | { .compatible = "brcm,brcmnand-v5.0" }, |
| 2449 | { .compatible = "brcm,brcmnand-v6.0" }, |
| 2450 | { .compatible = "brcm,brcmnand-v6.1" }, |
| 2451 | { .compatible = "brcm,brcmnand-v6.2" }, |
| 2452 | { .compatible = "brcm,brcmnand-v7.0" }, |
| 2453 | { .compatible = "brcm,brcmnand-v7.1" }, |
| 2454 | { .compatible = "brcm,brcmnand-v7.2" }, |
| 2455 | {}, |
| 2456 | }; |
| 2457 | MODULE_DEVICE_TABLE(of, brcmnand_of_match); |
| 2458 | #endif /* __UBOOT__ */ |
| 2459 | |
| 2460 | /*********************************************************************** |
| 2461 | * Platform driver setup (per controller) |
| 2462 | ***********************************************************************/ |
| 2463 | |
| 2464 | #ifndef __UBOOT__ |
| 2465 | int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) |
| 2466 | #else |
| 2467 | int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc) |
| 2468 | #endif /* __UBOOT__ */ |
| 2469 | { |
| 2470 | #ifndef __UBOOT__ |
| 2471 | struct device *dev = &pdev->dev; |
| 2472 | struct device_node *dn = dev->of_node, *child; |
| 2473 | #else |
| 2474 | ofnode child; |
| 2475 | struct udevice *pdev = dev; |
| 2476 | #endif /* __UBOOT__ */ |
| 2477 | struct brcmnand_controller *ctrl; |
| 2478 | #ifndef __UBOOT__ |
| 2479 | struct resource *res; |
| 2480 | #else |
| 2481 | struct resource res; |
| 2482 | #endif /* __UBOOT__ */ |
| 2483 | int ret; |
| 2484 | |
| 2485 | #ifndef __UBOOT__ |
| 2486 | /* We only support device-tree instantiation */ |
| 2487 | if (!dn) |
| 2488 | return -ENODEV; |
| 2489 | |
| 2490 | if (!of_match_node(brcmnand_of_match, dn)) |
| 2491 | return -ENODEV; |
| 2492 | #endif /* __UBOOT__ */ |
| 2493 | |
| 2494 | ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); |
| 2495 | if (!ctrl) |
| 2496 | return -ENOMEM; |
| 2497 | |
| 2498 | #ifndef __UBOOT__ |
| 2499 | dev_set_drvdata(dev, ctrl); |
| 2500 | #else |
| 2501 | /* |
| 2502 | * in u-boot, the data for the driver is allocated before probing |
| 2503 | * so to keep the reference to ctrl, we store it in the variable soc |
| 2504 | */ |
| 2505 | soc->ctrl = ctrl; |
| 2506 | #endif /* __UBOOT__ */ |
| 2507 | ctrl->dev = dev; |
| 2508 | |
| 2509 | init_completion(&ctrl->done); |
| 2510 | init_completion(&ctrl->dma_done); |
| 2511 | nand_hw_control_init(&ctrl->controller); |
| 2512 | INIT_LIST_HEAD(&ctrl->host_list); |
| 2513 | |
Philippe Reynes | 7f28cf6 | 2019-03-15 15:14:37 +0100 | [diff] [blame] | 2514 | /* Is parameter page in big endian ? */ |
| 2515 | ctrl->parameter_page_big_endian = |
| 2516 | dev_read_u32_default(dev, "parameter-page-big-endian", 1); |
| 2517 | |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 2518 | /* NAND register range */ |
| 2519 | #ifndef __UBOOT__ |
| 2520 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2521 | ctrl->nand_base = devm_ioremap_resource(dev, res); |
| 2522 | #else |
| 2523 | dev_read_resource(pdev, 0, &res); |
| 2524 | ctrl->nand_base = devm_ioremap(pdev, res.start, resource_size(&res)); |
| 2525 | #endif |
| 2526 | if (IS_ERR(ctrl->nand_base)) |
| 2527 | return PTR_ERR(ctrl->nand_base); |
| 2528 | |
| 2529 | /* Enable clock before using NAND registers */ |
| 2530 | ctrl->clk = devm_clk_get(dev, "nand"); |
| 2531 | if (!IS_ERR(ctrl->clk)) { |
| 2532 | ret = clk_prepare_enable(ctrl->clk); |
| 2533 | if (ret) |
| 2534 | return ret; |
| 2535 | } else { |
| 2536 | ret = PTR_ERR(ctrl->clk); |
| 2537 | if (ret == -EPROBE_DEFER) |
| 2538 | return ret; |
| 2539 | |
| 2540 | ctrl->clk = NULL; |
| 2541 | } |
| 2542 | |
| 2543 | /* Initialize NAND revision */ |
| 2544 | ret = brcmnand_revision_init(ctrl); |
| 2545 | if (ret) |
| 2546 | goto err; |
| 2547 | |
| 2548 | /* |
| 2549 | * Most chips have this cache at a fixed offset within 'nand' block. |
| 2550 | * Some must specify this region separately. |
| 2551 | */ |
| 2552 | #ifndef __UBOOT__ |
| 2553 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); |
| 2554 | if (res) { |
| 2555 | ctrl->nand_fc = devm_ioremap_resource(dev, res); |
| 2556 | if (IS_ERR(ctrl->nand_fc)) { |
| 2557 | ret = PTR_ERR(ctrl->nand_fc); |
| 2558 | goto err; |
| 2559 | } |
| 2560 | } else { |
| 2561 | ctrl->nand_fc = ctrl->nand_base + |
| 2562 | ctrl->reg_offsets[BRCMNAND_FC_BASE]; |
| 2563 | } |
| 2564 | #else |
| 2565 | if (!dev_read_resource_byname(pdev, "nand-cache", &res)) { |
| 2566 | ctrl->nand_fc = devm_ioremap(dev, res.start, |
| 2567 | resource_size(&res)); |
| 2568 | if (IS_ERR(ctrl->nand_fc)) { |
| 2569 | ret = PTR_ERR(ctrl->nand_fc); |
| 2570 | goto err; |
| 2571 | } |
| 2572 | } else { |
| 2573 | ctrl->nand_fc = ctrl->nand_base + |
| 2574 | ctrl->reg_offsets[BRCMNAND_FC_BASE]; |
| 2575 | } |
| 2576 | #endif |
| 2577 | |
| 2578 | #ifndef __UBOOT__ |
| 2579 | /* FLASH_DMA */ |
| 2580 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); |
| 2581 | if (res) { |
| 2582 | ctrl->flash_dma_base = devm_ioremap_resource(dev, res); |
| 2583 | if (IS_ERR(ctrl->flash_dma_base)) { |
| 2584 | ret = PTR_ERR(ctrl->flash_dma_base); |
| 2585 | goto err; |
| 2586 | } |
| 2587 | |
| 2588 | flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */ |
| 2589 | flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); |
| 2590 | |
| 2591 | /* Allocate descriptor(s) */ |
| 2592 | ctrl->dma_desc = dmam_alloc_coherent(dev, |
| 2593 | sizeof(*ctrl->dma_desc), |
| 2594 | &ctrl->dma_pa, GFP_KERNEL); |
| 2595 | if (!ctrl->dma_desc) { |
| 2596 | ret = -ENOMEM; |
| 2597 | goto err; |
| 2598 | } |
| 2599 | |
| 2600 | ctrl->dma_irq = platform_get_irq(pdev, 1); |
| 2601 | if ((int)ctrl->dma_irq < 0) { |
| 2602 | dev_err(dev, "missing FLASH_DMA IRQ\n"); |
| 2603 | ret = -ENODEV; |
| 2604 | goto err; |
| 2605 | } |
| 2606 | |
| 2607 | ret = devm_request_irq(dev, ctrl->dma_irq, |
| 2608 | brcmnand_dma_irq, 0, DRV_NAME, |
| 2609 | ctrl); |
| 2610 | if (ret < 0) { |
| 2611 | dev_err(dev, "can't allocate IRQ %d: error %d\n", |
| 2612 | ctrl->dma_irq, ret); |
| 2613 | goto err; |
| 2614 | } |
| 2615 | |
| 2616 | dev_info(dev, "enabling FLASH_DMA\n"); |
| 2617 | } |
| 2618 | #endif /* __UBOOT__ */ |
| 2619 | |
| 2620 | /* Disable automatic device ID config, direct addressing */ |
| 2621 | brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, |
| 2622 | CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0); |
| 2623 | /* Disable XOR addressing */ |
| 2624 | brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); |
| 2625 | |
Philippe Reynes | 77669af | 2019-03-15 15:14:38 +0100 | [diff] [blame] | 2626 | /* Read the write-protect configuration in the device tree */ |
| 2627 | wp_on = dev_read_u32_default(dev, "write-protect", wp_on); |
| 2628 | |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 2629 | if (ctrl->features & BRCMNAND_HAS_WP) { |
| 2630 | /* Permanently disable write protection */ |
| 2631 | if (wp_on == 2) |
| 2632 | brcmnand_set_wp(ctrl, false); |
| 2633 | } else { |
| 2634 | wp_on = 0; |
| 2635 | } |
| 2636 | |
| 2637 | #ifndef __UBOOT__ |
| 2638 | /* IRQ */ |
| 2639 | ctrl->irq = platform_get_irq(pdev, 0); |
| 2640 | if ((int)ctrl->irq < 0) { |
| 2641 | dev_err(dev, "no IRQ defined\n"); |
| 2642 | ret = -ENODEV; |
| 2643 | goto err; |
| 2644 | } |
| 2645 | |
| 2646 | /* |
| 2647 | * Some SoCs integrate this controller (e.g., its interrupt bits) in |
| 2648 | * interesting ways |
| 2649 | */ |
| 2650 | if (soc) { |
| 2651 | ctrl->soc = soc; |
| 2652 | |
| 2653 | ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, |
| 2654 | DRV_NAME, ctrl); |
| 2655 | |
| 2656 | /* Enable interrupt */ |
| 2657 | ctrl->soc->ctlrdy_ack(ctrl->soc); |
| 2658 | ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); |
| 2659 | } else { |
| 2660 | /* Use standard interrupt infrastructure */ |
| 2661 | ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, |
| 2662 | DRV_NAME, ctrl); |
| 2663 | } |
| 2664 | if (ret < 0) { |
| 2665 | dev_err(dev, "can't allocate IRQ %d: error %d\n", |
| 2666 | ctrl->irq, ret); |
| 2667 | goto err; |
| 2668 | } |
| 2669 | #endif /* __UBOOT__ */ |
| 2670 | |
| 2671 | #ifndef __UBOOT__ |
| 2672 | for_each_available_child_of_node(dn, child) { |
| 2673 | if (of_device_is_compatible(child, "brcm,nandcs")) { |
| 2674 | struct brcmnand_host *host; |
| 2675 | |
| 2676 | host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); |
| 2677 | if (!host) { |
| 2678 | of_node_put(child); |
| 2679 | ret = -ENOMEM; |
| 2680 | goto err; |
| 2681 | } |
| 2682 | host->pdev = pdev; |
| 2683 | host->ctrl = ctrl; |
| 2684 | |
| 2685 | ret = brcmnand_init_cs(host, child); |
| 2686 | if (ret) { |
| 2687 | devm_kfree(dev, host); |
| 2688 | continue; /* Try all chip-selects */ |
| 2689 | } |
| 2690 | |
| 2691 | list_add_tail(&host->node, &ctrl->host_list); |
| 2692 | } |
| 2693 | } |
| 2694 | #else |
| 2695 | ofnode_for_each_subnode(child, dev_ofnode(dev)) { |
| 2696 | if (ofnode_device_is_compatible(child, "brcm,nandcs")) { |
| 2697 | struct brcmnand_host *host; |
| 2698 | |
| 2699 | host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); |
| 2700 | if (!host) { |
| 2701 | ret = -ENOMEM; |
| 2702 | goto err; |
| 2703 | } |
| 2704 | host->pdev = pdev; |
| 2705 | host->ctrl = ctrl; |
| 2706 | |
| 2707 | ret = brcmnand_init_cs(host, child); |
| 2708 | if (ret) { |
| 2709 | devm_kfree(dev, host); |
| 2710 | continue; /* Try all chip-selects */ |
| 2711 | } |
| 2712 | |
| 2713 | list_add_tail(&host->node, &ctrl->host_list); |
| 2714 | } |
| 2715 | } |
| 2716 | #endif /* __UBOOT__ */ |
| 2717 | |
Álvaro Fernández Rojas | d8ae875 | 2020-04-02 10:37:52 +0200 | [diff] [blame] | 2718 | /* No chip-selects could initialize properly */ |
| 2719 | if (list_empty(&ctrl->host_list)) { |
| 2720 | ret = -ENODEV; |
| 2721 | goto err; |
| 2722 | } |
| 2723 | |
| 2724 | return 0; |
| 2725 | |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 2726 | err: |
| 2727 | #ifndef __UBOOT__ |
| 2728 | clk_disable_unprepare(ctrl->clk); |
| 2729 | #else |
| 2730 | if (ctrl->clk) |
| 2731 | clk_disable(ctrl->clk); |
| 2732 | #endif /* __UBOOT__ */ |
| 2733 | return ret; |
Philippe Reynes | 5aa6cfb | 2019-03-15 15:14:36 +0100 | [diff] [blame] | 2734 | } |
| 2735 | EXPORT_SYMBOL_GPL(brcmnand_probe); |
| 2736 | |
| 2737 | #ifndef __UBOOT__ |
| 2738 | int brcmnand_remove(struct platform_device *pdev) |
| 2739 | { |
| 2740 | struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); |
| 2741 | struct brcmnand_host *host; |
| 2742 | |
| 2743 | list_for_each_entry(host, &ctrl->host_list, node) |
| 2744 | nand_release(nand_to_mtd(&host->chip)); |
| 2745 | |
| 2746 | clk_disable_unprepare(ctrl->clk); |
| 2747 | |
| 2748 | dev_set_drvdata(&pdev->dev, NULL); |
| 2749 | |
| 2750 | return 0; |
| 2751 | } |
| 2752 | #else |
| 2753 | int brcmnand_remove(struct udevice *pdev) |
| 2754 | { |
| 2755 | return 0; |
| 2756 | } |
| 2757 | #endif /* __UBOOT__ */ |
| 2758 | EXPORT_SYMBOL_GPL(brcmnand_remove); |
| 2759 | |
| 2760 | MODULE_LICENSE("GPL v2"); |
| 2761 | MODULE_AUTHOR("Kevin Cernekee"); |
| 2762 | MODULE_AUTHOR("Brian Norris"); |
| 2763 | MODULE_DESCRIPTION("NAND driver for Broadcom chips"); |
| 2764 | MODULE_ALIAS("platform:brcmnand"); |