Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 2 | /* |
Egli, Samuel | 097951b | 2014-05-05 16:50:43 +0200 | [diff] [blame] | 3 | * pinmux setup for siemens draco board |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 4 | * |
| 5 | * (C) Copyright 2013 Siemens Schweiz AG |
| 6 | * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 7 | * |
| 8 | * Based on: |
| 9 | * u-boot:/board/ti/am335x/mux.c |
Nishanth Menon | eaa39c6 | 2023-11-01 15:56:03 -0500 | [diff] [blame] | 10 | * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 11 | */ |
| 12 | |
Enrico Leto | fce9179 | 2024-01-24 15:43:54 +0100 | [diff] [blame] | 13 | #include <asm/io.h> |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 14 | #include <asm/arch/sys_proto.h> |
| 15 | #include <asm/arch/hardware.h> |
| 16 | #include <asm/arch/mux.h> |
Enrico Leto | 32f433f | 2024-01-24 15:43:50 +0100 | [diff] [blame] | 17 | #include "eeprom.h" |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 18 | |
| 19 | static struct module_pin_mux uart0_pin_mux[] = { |
| 20 | {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ |
| 21 | {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ |
| 22 | {-1}, |
| 23 | }; |
| 24 | |
| 25 | static struct module_pin_mux uart3_pin_mux[] = { |
| 26 | {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ |
| 27 | {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ |
| 28 | {-1}, |
| 29 | }; |
| 30 | |
| 31 | static struct module_pin_mux i2c0_pin_mux[] = { |
| 32 | {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | |
| 33 | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ |
| 34 | {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | |
| 35 | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ |
| 36 | {-1}, |
| 37 | }; |
| 38 | |
| 39 | static struct module_pin_mux nand_pin_mux[] = { |
| 40 | {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ |
| 41 | {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ |
| 42 | {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ |
| 43 | {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ |
| 44 | {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ |
| 45 | {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ |
| 46 | {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ |
| 47 | {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ |
| 48 | {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ |
| 49 | {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ |
| 50 | {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ |
Heiko Schocher | cbec11a | 2016-06-07 08:55:45 +0200 | [diff] [blame] | 51 | {OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN}, /* NAND_CS1 */ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 52 | {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ |
| 53 | {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ |
| 54 | {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ |
| 55 | {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ |
| 56 | {-1}, |
| 57 | }; |
| 58 | |
| 59 | static struct module_pin_mux gpios_pin_mux[] = { |
| 60 | /* DFU button GPIO0_27*/ |
Heiko Schocher | d17c3fc | 2015-06-16 14:59:34 +0200 | [diff] [blame] | 61 | {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 62 | {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */ |
| 63 | {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */ |
Samuel Egli | 8069bfe | 2013-11-04 14:05:03 +0100 | [diff] [blame] | 64 | /* Triacs in HW Rev 2 */ |
| 65 | {OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y5 GPIO0_12*/ |
| 66 | {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/ |
| 67 | {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/ |
| 68 | /* Triacs initial HW Rev */ |
Samuel Egli | 8069bfe | 2013-11-04 14:05:03 +0100 | [diff] [blame] | 69 | {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */ |
| 70 | {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */ |
| 71 | {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */ |
| 72 | {OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_10 Y4 */ |
| 73 | {OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS}, /* 2_1 Y5 */ |
| 74 | {OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 3_8 Y6 */ |
| 75 | {OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_15 Y7 */ |
| 76 | /* Remaining pins that were not used in this file */ |
| 77 | {OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 78 | {OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 79 | {OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 80 | {OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 81 | {OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 82 | {OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 83 | {OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 84 | {OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 85 | {OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 86 | {OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 87 | {OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 88 | {OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 89 | {OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 90 | {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 91 | {OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 92 | {OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 93 | {OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 94 | {OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 95 | {OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 96 | {OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 97 | {OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 98 | {OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 99 | {OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 100 | {OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 101 | {OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 102 | {OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 103 | {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 104 | {OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 105 | {OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 106 | {OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 107 | {OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 108 | {OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 109 | {OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 110 | {OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 111 | {OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 112 | {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 113 | {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 114 | {OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 115 | {OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 116 | {OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 117 | {OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 118 | {OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 119 | {OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 120 | {OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 121 | {OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 122 | {OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 123 | {OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 124 | {OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 125 | {OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 126 | {OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 127 | {OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 128 | {OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 129 | {OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 130 | {OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 131 | {OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 132 | {OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 133 | {OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 134 | {OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 135 | {OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 136 | {OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 137 | {OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 138 | {OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 139 | {OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 140 | {OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 141 | {OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 142 | {OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 143 | {OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 144 | {OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 145 | {OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 146 | {OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 147 | {OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 148 | {OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 149 | {OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 150 | {OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 151 | {OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 152 | {OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 153 | {OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 154 | {OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 155 | {OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 156 | {OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 157 | {OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 158 | {OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 159 | {OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 160 | {OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 161 | {OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 162 | {OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 163 | {OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 164 | {OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 165 | {OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 166 | {OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 167 | {OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 168 | {OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 169 | {OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 170 | {OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 171 | {OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 172 | {OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 173 | {OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 174 | {OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 175 | {OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 176 | {OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 177 | {OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 178 | {OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 179 | {OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 180 | {OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 181 | {OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 182 | {OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 183 | {OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 184 | {OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 185 | {OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 186 | {OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 187 | {OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 188 | {OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 189 | {OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 190 | {OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 191 | {OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 192 | {OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 193 | {OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 194 | {OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 195 | {OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 196 | {OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 197 | {OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 198 | {OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 199 | {OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 200 | {OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 201 | {OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 202 | {OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 203 | {OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 204 | {OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 205 | {OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 206 | {OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 207 | {OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 208 | {OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 209 | {OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 210 | {OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 211 | {OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 212 | {OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 213 | {OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 214 | {OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 215 | {OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 216 | {OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 217 | {OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 218 | {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 219 | {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS}, |
| 220 | {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS}, |
Stefan Roese | 7d654ab | 2014-02-25 11:07:22 +0100 | [diff] [blame] | 221 | /* nRST for SMSC LAN9303 switch - GPIO2_24 */ |
Heiko Schocher | d17c3fc | 2015-06-16 14:59:34 +0200 | [diff] [blame] | 222 | {OFFSET(lcd_pclk), MODE(7) | PULLUDEN | PULLUP_EN }, /* LAN9303 nRST */ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 223 | {-1}, |
| 224 | }; |
| 225 | |
| 226 | static struct module_pin_mux ethernet_pin_mux[] = { |
| 227 | {OFFSET(mii1_col), (MODE(3) | RXACTIVE)}, |
| 228 | {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, |
| 229 | {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, |
| 230 | {OFFSET(mii1_txen), (MODE(1))}, |
| 231 | {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)}, |
| 232 | {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, |
| 233 | {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, |
| 234 | {OFFSET(mii1_txd1), (MODE(1))}, |
| 235 | {OFFSET(mii1_txd0), (MODE(1))}, |
| 236 | {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)}, |
| 237 | {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)}, |
| 238 | {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)}, |
| 239 | {OFFSET(mii1_rxd2), (MODE(1))}, |
| 240 | {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, |
| 241 | {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, |
| 242 | {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, |
| 243 | {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, |
| 244 | {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, |
| 245 | {-1}, |
| 246 | }; |
| 247 | |
| 248 | void enable_uart0_pin_mux(void) |
| 249 | { |
| 250 | configure_module_pin_mux(uart0_pin_mux); |
| 251 | } |
| 252 | |
| 253 | void enable_uart3_pin_mux(void) |
| 254 | { |
| 255 | configure_module_pin_mux(uart3_pin_mux); |
| 256 | } |
| 257 | |
| 258 | void enable_i2c0_pin_mux(void) |
| 259 | { |
| 260 | configure_module_pin_mux(i2c0_pin_mux); |
| 261 | } |
| 262 | |
| 263 | void enable_board_pin_mux(void) |
| 264 | { |
| 265 | enable_uart3_pin_mux(); |
| 266 | configure_module_pin_mux(nand_pin_mux); |
| 267 | configure_module_pin_mux(ethernet_pin_mux); |
| 268 | configure_module_pin_mux(gpios_pin_mux); |
| 269 | } |