wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 1 | /* |
wdenk | 8d5d28a | 2005-04-02 22:37:54 +0000 | [diff] [blame] | 2 | * (C) Copyright 2000-2005 |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * board/config.h - configuration options, board specific |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H |
| 30 | |
| 31 | /* |
| 32 | * High Level Configuration Options |
| 33 | * (easy to change) |
| 34 | */ |
| 35 | |
| 36 | #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ |
| 37 | #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ |
dzu | b02ed68 | 2003-10-19 21:43:26 +0000 | [diff] [blame] | 38 | #define CONFIG_NSCU 1 |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 39 | |
| 40 | #define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ |
| 41 | |
| 42 | #define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ |
| 43 | |
| 44 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
| 45 | |
| 46 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 47 | |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 48 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
| 49 | |
| 50 | #define CONFIG_PREBOOT "echo;" \ |
Wolfgang Denk | 1baed66 | 2008-03-03 12:16:44 +0100 | [diff] [blame] | 51 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 52 | "echo" |
| 53 | |
| 54 | #undef CONFIG_BOOTARGS |
| 55 | |
| 56 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 57 | "netdev=eth0\0" \ |
| 58 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 59 | "nfsroot=${serverip}:${rootpath}\0" \ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 60 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 61 | "addip=setenv bootargs ${bootargs} " \ |
| 62 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 63 | ":${hostname}:${netdev}:off panic=1\0" \ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 64 | "flash_nfs=run nfsargs addip;" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 65 | "bootm ${kernel_addr}\0" \ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 66 | "flash_self=run ramargs addip;" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 67 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 68 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 69 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
| 70 | "bootfile=/tftpboot/NSCU/uImage\0" \ |
| 71 | "kernel_addr=40080000\0" \ |
| 72 | "ramdisk_addr=40180000\0" \ |
| 73 | "" |
| 74 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 75 | |
wdenk | 3cc599e | 2004-08-01 13:09:47 +0000 | [diff] [blame] | 76 | #define CONFIG_MISC_INIT_R 1 |
| 77 | |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 78 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 79 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| 80 | |
| 81 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 82 | |
| 83 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
| 84 | |
| 85 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
| 86 | |
Jon Loeliger | df5f544 | 2007-07-09 21:24:19 -0500 | [diff] [blame] | 87 | /* |
| 88 | * BOOTP options |
| 89 | */ |
| 90 | #define CONFIG_BOOTP_SUBNETMASK |
| 91 | #define CONFIG_BOOTP_GATEWAY |
| 92 | #define CONFIG_BOOTP_HOSTNAME |
| 93 | #define CONFIG_BOOTP_BOOTPATH |
| 94 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 95 | |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 96 | |
| 97 | #define CONFIG_MAC_PARTITION |
| 98 | #define CONFIG_DOS_PARTITION |
| 99 | |
| 100 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
| 101 | |
wdenk | 0a65855 | 2003-08-05 17:43:17 +0000 | [diff] [blame] | 102 | #define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ |
| 103 | |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 104 | |
Jon Loeliger | f835bec | 2007-07-08 14:21:43 -0500 | [diff] [blame] | 105 | /* |
| 106 | * Command line configuration. |
| 107 | */ |
| 108 | #include <config_cmd_default.h> |
| 109 | |
| 110 | #define CONFIG_CMD_ASKENV |
| 111 | #define CONFIG_CMD_DATE |
| 112 | #define CONFIG_CMD_DHCP |
| 113 | #define CONFIG_CMD_IDE |
| 114 | #define CONFIG_CMD_NFS |
| 115 | #define CONFIG_CMD_SNTP |
| 116 | |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 117 | |
| 118 | /* |
| 119 | * Miscellaneous configurable options |
| 120 | */ |
| 121 | #define CFG_LONGHELP /* undef to save memory */ |
| 122 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 123 | |
| 124 | #if 0 |
| 125 | #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ |
| 126 | #endif |
| 127 | #ifdef CFG_HUSH_PARSER |
| 128 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 129 | #endif |
| 130 | |
Jon Loeliger | f835bec | 2007-07-08 14:21:43 -0500 | [diff] [blame] | 131 | #if defined(CONFIG_CMD_KGDB) |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 132 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 133 | #else |
| 134 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 135 | #endif |
| 136 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 137 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 138 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 139 | |
| 140 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
| 141 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
| 142 | |
| 143 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
| 144 | |
| 145 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 146 | |
| 147 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 148 | |
| 149 | /* |
| 150 | * Low Level Configuration Settings |
| 151 | * (address mappings, register initial values, etc.) |
| 152 | * You should know what you are doing if you make changes here. |
| 153 | */ |
| 154 | /*----------------------------------------------------------------------- |
| 155 | * Internal Memory Mapped Register |
| 156 | */ |
| 157 | #define CFG_IMMR 0xFFF00000 |
| 158 | |
| 159 | /*----------------------------------------------------------------------- |
| 160 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 161 | */ |
| 162 | #define CFG_INIT_RAM_ADDR CFG_IMMR |
| 163 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
| 164 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
| 165 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 166 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 167 | |
| 168 | /*----------------------------------------------------------------------- |
| 169 | * Start addresses for the final memory configuration |
| 170 | * (Set up by the startup code) |
| 171 | * Please note that CFG_SDRAM_BASE _must_ start at 0 |
| 172 | */ |
| 173 | #define CFG_SDRAM_BASE 0x00000000 |
| 174 | #define CFG_FLASH_BASE 0x40000000 |
| 175 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 176 | #define CFG_MONITOR_BASE CFG_FLASH_BASE |
| 177 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
| 178 | |
| 179 | /* |
| 180 | * For booting Linux, the board info and command line data |
| 181 | * have to be in the first 8 MB of memory, since this is |
| 182 | * the maximum mapped by the Linux kernel during initialization. |
| 183 | */ |
| 184 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 185 | |
| 186 | /*----------------------------------------------------------------------- |
| 187 | * FLASH organization |
| 188 | */ |
| 189 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 190 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
| 191 | |
| 192 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 193 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
| 194 | |
| 195 | #define CFG_ENV_IS_IN_FLASH 1 |
| 196 | #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
| 197 | #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ |
| 198 | #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ |
| 199 | |
| 200 | /* Address and size of Redundant Environment Sector */ |
| 201 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) |
| 202 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
| 203 | |
| 204 | /*----------------------------------------------------------------------- |
| 205 | * Hardware Information Block |
| 206 | */ |
| 207 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
| 208 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
| 209 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
| 210 | |
| 211 | /*----------------------------------------------------------------------- |
| 212 | * Cache Configuration |
| 213 | */ |
| 214 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
Jon Loeliger | f835bec | 2007-07-08 14:21:43 -0500 | [diff] [blame] | 215 | #if defined(CONFIG_CMD_KGDB) |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 216 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
| 217 | #endif |
| 218 | |
| 219 | /*----------------------------------------------------------------------- |
| 220 | * SYPCR - System Protection Control 11-9 |
| 221 | * SYPCR can only be written once after reset! |
| 222 | *----------------------------------------------------------------------- |
| 223 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
| 224 | */ |
| 225 | #if defined(CONFIG_WATCHDOG) |
| 226 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
| 227 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 228 | #else |
| 229 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
| 230 | #endif |
| 231 | |
| 232 | /*----------------------------------------------------------------------- |
| 233 | * SIUMCR - SIU Module Configuration 11-6 |
| 234 | *----------------------------------------------------------------------- |
| 235 | * PCMCIA config., multi-function pin tri-state |
| 236 | */ |
| 237 | #ifndef CONFIG_CAN_DRIVER |
| 238 | #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
| 239 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
| 240 | #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
| 241 | #endif /* CONFIG_CAN_DRIVER */ |
| 242 | |
| 243 | /*----------------------------------------------------------------------- |
| 244 | * TBSCR - Time Base Status and Control 11-26 |
| 245 | *----------------------------------------------------------------------- |
| 246 | * Clear Reference Interrupt Status, Timebase freezing enabled |
| 247 | */ |
| 248 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
| 249 | |
| 250 | /*----------------------------------------------------------------------- |
| 251 | * RTCSC - Real-Time Clock Status and Control Register 11-27 |
| 252 | *----------------------------------------------------------------------- |
| 253 | */ |
| 254 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
| 255 | |
| 256 | /*----------------------------------------------------------------------- |
| 257 | * PISCR - Periodic Interrupt Status and Control 11-31 |
| 258 | *----------------------------------------------------------------------- |
| 259 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
| 260 | */ |
| 261 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) |
| 262 | |
| 263 | /*----------------------------------------------------------------------- |
| 264 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
| 265 | *----------------------------------------------------------------------- |
| 266 | * Reset PLL lock status sticky bit, timer expired status bit and timer |
| 267 | * interrupt status bit |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 268 | */ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 269 | #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 270 | |
| 271 | /*----------------------------------------------------------------------- |
| 272 | * SCCR - System Clock and reset Control Register 15-27 |
| 273 | *----------------------------------------------------------------------- |
| 274 | * Set clock output, timebase and RTC source and divider, |
| 275 | * power management and some other internal clocks |
| 276 | */ |
| 277 | #define SCCR_MASK SCCR_EBDF11 |
wdenk | 3cc599e | 2004-08-01 13:09:47 +0000 | [diff] [blame] | 278 | #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 279 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
| 280 | SCCR_DFALCD00) |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 281 | |
| 282 | /*----------------------------------------------------------------------- |
| 283 | * PCMCIA stuff |
| 284 | *----------------------------------------------------------------------- |
| 285 | * |
| 286 | */ |
dzu | b02ed68 | 2003-10-19 21:43:26 +0000 | [diff] [blame] | 287 | /* NSCU use both slots, SLOT_A as "primary". */ |
| 288 | #define CONFIG_PCMCIA_SLOT_A 1 |
| 289 | |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 290 | #define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
| 291 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
| 292 | #define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
| 293 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
| 294 | #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
| 295 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
| 296 | #define CFG_PCMCIA_IO_ADDR (0xEC000000) |
| 297 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 298 | #define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ |
| 299 | #define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ |
wdenk | dee058f | 2004-09-27 20:20:11 +0000 | [diff] [blame] | 300 | #undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 301 | |
| 302 | /*----------------------------------------------------------------------- |
| 303 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
| 304 | *----------------------------------------------------------------------- |
| 305 | */ |
| 306 | |
| 307 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
| 308 | |
| 309 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
| 310 | #undef CONFIG_IDE_LED /* LED for ide not supported */ |
| 311 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
| 312 | |
dzu | b02ed68 | 2003-10-19 21:43:26 +0000 | [diff] [blame] | 313 | #define CFG_IDE_MAXBUS 2 /* max. 2 IDE buses */ |
| 314 | #define CFG_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 315 | |
| 316 | #define CFG_ATA_IDE0_OFFSET 0x0000 |
dzu | b02ed68 | 2003-10-19 21:43:26 +0000 | [diff] [blame] | 317 | #define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) /* starts @ 4th window */ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 318 | |
| 319 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
| 320 | |
| 321 | /* Offset for data I/O */ |
| 322 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
| 323 | |
| 324 | /* Offset for normal register accesses */ |
| 325 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
| 326 | |
| 327 | /* Offset for alternate registers */ |
| 328 | #define CFG_ATA_ALT_OFFSET 0x0100 |
| 329 | |
| 330 | /*----------------------------------------------------------------------- |
| 331 | * |
| 332 | *----------------------------------------------------------------------- |
| 333 | * |
| 334 | */ |
| 335 | #define CFG_DER 0 |
| 336 | |
| 337 | /* |
| 338 | * Init Memory Controller: |
| 339 | * |
| 340 | * BR0/1 and OR0/1 (FLASH) |
| 341 | */ |
| 342 | |
| 343 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
| 344 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
| 345 | |
| 346 | /* used to re-map FLASH both when starting from SRAM or FLASH: |
| 347 | * restrict access enough to keep SRAM working (if any) |
| 348 | * but not too much to meddle with FLASH accesses |
| 349 | */ |
| 350 | #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
| 351 | #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
| 352 | |
| 353 | /* |
| 354 | * FLASH timing: |
| 355 | */ |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 356 | #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
| 357 | OR_SCY_3_CLK | OR_EHTR | OR_BI) |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 358 | |
| 359 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
| 360 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
| 361 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
| 362 | |
| 363 | #define CFG_OR1_REMAP CFG_OR0_REMAP |
| 364 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM |
| 365 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
| 366 | |
| 367 | /* |
| 368 | * BR2/3 and OR2/3 (SDRAM) |
| 369 | * |
| 370 | */ |
| 371 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
| 372 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
| 373 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
| 374 | |
| 375 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
| 376 | #define CFG_OR_TIMING_SDRAM 0x00000A00 |
| 377 | |
| 378 | #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) |
| 379 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
| 380 | |
| 381 | #ifndef CONFIG_CAN_DRIVER |
| 382 | #define CFG_OR3_PRELIM CFG_OR2_PRELIM |
| 383 | #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
| 384 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
| 385 | #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
| 386 | #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
| 387 | #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) |
| 388 | #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ |
| 389 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
| 390 | #endif /* CONFIG_CAN_DRIVER */ |
| 391 | |
wdenk | 0a65855 | 2003-08-05 17:43:17 +0000 | [diff] [blame] | 392 | #ifdef CONFIG_ISP1362_USB |
| 393 | #define CFG_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ |
| 394 | #define CFG_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
| 395 | #define CFG_OR5_ISP1362 (CFG_ISP1362_OR_AM | OR_CSNT_SAM | \ |
| 396 | OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) |
| 397 | #define CFG_BR5_ISP1362 ((CFG_ISP1362_BASE & BR_BA_MSK) | \ |
| 398 | BR_PS_16 | BR_MS_GPCM | BR_V ) |
| 399 | #endif /* CONFIG_ISP1362_USB */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 400 | |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 401 | /* |
| 402 | * Memory Periodic Timer Prescaler |
| 403 | * |
| 404 | * The Divider for PTA (refresh timer) configuration is based on an |
| 405 | * example SDRAM configuration (64 MBit, one bank). The adjustment to |
| 406 | * the number of chip selects (NCS) and the actually needed refresh |
| 407 | * rate is done by setting MPTPR. |
| 408 | * |
| 409 | * PTA is calculated from |
| 410 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
| 411 | * |
| 412 | * gclk CPU clock (not bus clock!) |
| 413 | * Trefresh Refresh cycle * 4 (four word bursts used) |
| 414 | * |
| 415 | * 4096 Rows from SDRAM example configuration |
| 416 | * 1000 factor s -> ms |
| 417 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
| 418 | * 4 Number of refresh cycles per period |
| 419 | * 64 Refresh cycle in ms per number of rows |
| 420 | * -------------------------------------------- |
| 421 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
| 422 | * |
| 423 | * 50 MHz => 50.000.000 / Divider = 98 |
| 424 | * 66 Mhz => 66.000.000 / Divider = 129 |
| 425 | * 80 Mhz => 80.000.000 / Divider = 156 |
| 426 | */ |
wdenk | 3cc599e | 2004-08-01 13:09:47 +0000 | [diff] [blame] | 427 | |
| 428 | #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
| 429 | #define CFG_MAMR_PTA 98 |
wdenk | 6914128 | 2003-07-07 20:07:54 +0000 | [diff] [blame] | 430 | |
| 431 | /* |
| 432 | * For 16 MBit, refresh rates could be 31.3 us |
| 433 | * (= 64 ms / 2K = 125 / quad bursts). |
| 434 | * For a simpler initialization, 15.6 us is used instead. |
| 435 | * |
| 436 | * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
| 437 | * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
| 438 | */ |
| 439 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
| 440 | #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
| 441 | |
| 442 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
| 443 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
| 444 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
| 445 | |
| 446 | /* |
| 447 | * MAMR settings for SDRAM |
| 448 | */ |
| 449 | |
| 450 | /* 8 column SDRAM */ |
| 451 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| 452 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
| 453 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
| 454 | /* 9 column SDRAM */ |
| 455 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| 456 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
| 457 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
| 458 | |
| 459 | |
| 460 | /* |
| 461 | * Internal Definitions |
| 462 | * |
| 463 | * Boot Flags |
| 464 | */ |
| 465 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 466 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 467 | |
| 468 | #undef CONFIG_SCC1_ENET |
| 469 | #define CONFIG_FEC_ENET |
| 470 | /* #define CONFIG_ETHPRIME "FEC ETHERNET" */ |
| 471 | |
| 472 | #endif /* __CONFIG_H */ |