stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001-2004 |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * board/config.h - configuration options, board specific |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H |
| 30 | |
| 31 | /* |
| 32 | * High Level Configuration Options |
| 33 | * (easy to change) |
| 34 | */ |
| 35 | |
| 36 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
| 37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
| 38 | #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ |
| 39 | #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ |
| 40 | |
| 41 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
| 42 | |
| 43 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
| 44 | |
| 45 | #define CONFIG_BAUDRATE 9600 |
| 46 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
| 47 | |
| 48 | #undef CONFIG_BOOTARGS |
| 49 | #undef CONFIG_BOOTCOMMAND |
| 50 | |
| 51 | #define CONFIG_PREBOOT /* enable preboot variable */ |
| 52 | |
| 53 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 54 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 55 | |
| 56 | #define CONFIG_MII 1 /* MII PHY management */ |
| 57 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
| 58 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
Matthias Fuchs | 196088b | 2007-06-24 17:41:21 +0200 | [diff] [blame] | 59 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
| 60 | |
| 61 | #define CONFIG_NET_MULTI 1 |
| 62 | #undef CONFIG_HAS_ETH1 |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 63 | |
| 64 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ |
| 65 | |
Jon Loeliger | 1cb2cb6 | 2007-07-09 21:16:53 -0500 | [diff] [blame] | 66 | /* |
| 67 | * BOOTP options |
| 68 | */ |
| 69 | #define CONFIG_BOOTP_SUBNETMASK |
| 70 | #define CONFIG_BOOTP_GATEWAY |
| 71 | #define CONFIG_BOOTP_HOSTNAME |
| 72 | #define CONFIG_BOOTP_BOOTPATH |
| 73 | #define CONFIG_BOOTP_DNS |
| 74 | #define CONFIG_BOOTP_DNS2 |
| 75 | #define CONFIG_BOOTP_SEND_HOSTNAME |
| 76 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 77 | |
Jon Loeliger | 8c5f4a4 | 2007-07-05 19:52:35 -0500 | [diff] [blame] | 78 | /* |
| 79 | * Command line configuration. |
| 80 | */ |
| 81 | #include <config_cmd_default.h> |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 82 | |
Jon Loeliger | 8c5f4a4 | 2007-07-05 19:52:35 -0500 | [diff] [blame] | 83 | #define CONFIG_CMD_DHCP |
| 84 | #define CONFIG_CMD_PCI |
| 85 | #define CONFIG_CMD_IRQ |
| 86 | #define CONFIG_CMD_IDE |
| 87 | #define CONFIG_CMD_FAT |
| 88 | #define CONFIG_CMD_ELF |
| 89 | #define CONFIG_CMD_DATE |
Jon Loeliger | 8c5f4a4 | 2007-07-05 19:52:35 -0500 | [diff] [blame] | 90 | #define CONFIG_CMD_I2C |
| 91 | #define CONFIG_CMD_MII |
| 92 | #define CONFIG_CMD_PING |
| 93 | #define CONFIG_CMD_BSP |
| 94 | #define CONFIG_CMD_EEPROM |
| 95 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 96 | #define CONFIG_MAC_PARTITION |
| 97 | #define CONFIG_DOS_PARTITION |
| 98 | |
| 99 | #define CONFIG_SUPPORT_VFAT |
| 100 | |
| 101 | #undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ |
| 102 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 103 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 104 | |
| 105 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
| 106 | |
| 107 | /* |
| 108 | * Miscellaneous configurable options |
| 109 | */ |
| 110 | #define CFG_LONGHELP /* undef to save memory */ |
| 111 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 112 | |
| 113 | #undef CFG_HUSH_PARSER /* use "hush" command parser */ |
| 114 | #ifdef CFG_HUSH_PARSER |
| 115 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 116 | #endif |
| 117 | |
Jon Loeliger | 8c5f4a4 | 2007-07-05 19:52:35 -0500 | [diff] [blame] | 118 | #if defined(CONFIG_CMD_KGDB) |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 119 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 120 | #else |
| 121 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 122 | #endif |
| 123 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 124 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 125 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 126 | |
| 127 | #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ |
| 128 | |
| 129 | #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
| 130 | |
| 131 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
| 132 | |
| 133 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
| 134 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
| 135 | |
| 136 | #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ |
| 137 | #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ |
| 138 | #define CFG_BASE_BAUD 691200 |
| 139 | |
| 140 | /* The following table includes the supported baudrates */ |
| 141 | #define CFG_BAUDRATE_TABLE \ |
| 142 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
| 143 | 57600, 115200, 230400, 460800, 921600 } |
| 144 | |
| 145 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
| 146 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
| 147 | |
| 148 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 149 | |
| 150 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
| 151 | |
| 152 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
| 153 | |
| 154 | /* Only interrupt boot if special string is typed */ |
| 155 | #define CONFIG_AUTOBOOT_KEYED 1 |
| 156 | #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n" |
| 157 | #undef CONFIG_AUTOBOOT_DELAY_STR |
| 158 | #undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ |
| 159 | #define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/ |
| 160 | |
| 161 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
| 162 | |
| 163 | #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
| 164 | |
| 165 | /*----------------------------------------------------------------------- |
| 166 | * PCI stuff |
| 167 | *----------------------------------------------------------------------- |
| 168 | */ |
| 169 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
| 170 | #define PCI_HOST_FORCE 1 /* configure as pci host */ |
| 171 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
| 172 | |
| 173 | #define CONFIG_PCI /* include pci support */ |
| 174 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
| 175 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 176 | /* resource configuration */ |
| 177 | |
| 178 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
| 179 | |
| 180 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ |
| 181 | |
| 182 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ |
| 183 | |
| 184 | #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
| 185 | #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ |
| 186 | #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ |
| 187 | #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ |
Stefan Roese | 1c671a9 | 2006-01-18 20:03:15 +0100 | [diff] [blame] | 188 | #define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ |
| 189 | #define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 190 | #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| 191 | #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ |
| 192 | #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ |
| 193 | #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
| 194 | |
| 195 | /*----------------------------------------------------------------------- |
| 196 | * IDE/ATA stuff |
| 197 | *----------------------------------------------------------------------- |
| 198 | */ |
| 199 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
| 200 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
| 201 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
| 202 | |
| 203 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
| 204 | #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ |
| 205 | |
| 206 | #define CFG_ATA_BASE_ADDR 0xF0100000 |
| 207 | #define CFG_ATA_IDE0_OFFSET 0x0000 |
| 208 | |
| 209 | #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
| 210 | #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ |
| 211 | #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ |
| 212 | |
| 213 | /*----------------------------------------------------------------------- |
| 214 | * Start addresses for the final memory configuration |
| 215 | * (Set up by the startup code) |
| 216 | * Please note that CFG_SDRAM_BASE _must_ start at 0 |
| 217 | */ |
| 218 | #define CFG_SDRAM_BASE 0x00000000 |
| 219 | #define CFG_FLASH_BASE 0xFFFC0000 |
| 220 | #define CFG_MONITOR_BASE CFG_FLASH_BASE |
| 221 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
| 222 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
| 223 | |
| 224 | /* |
| 225 | * For booting Linux, the board info and command line data |
| 226 | * have to be in the first 8 MB of memory, since this is |
| 227 | * the maximum mapped by the Linux kernel during initialization. |
| 228 | */ |
| 229 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 230 | /*----------------------------------------------------------------------- |
| 231 | * FLASH organization |
| 232 | */ |
| 233 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 234 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
| 235 | |
| 236 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 237 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
| 238 | |
| 239 | #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
| 240 | #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
| 241 | #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
| 242 | /* |
| 243 | * The following defines are added for buggy IOP480 byte interface. |
| 244 | * All other boards should use the standard values (CPCI405 etc.) |
| 245 | */ |
| 246 | #define CFG_FLASH_READ0 0x0000 /* 0 is standard */ |
| 247 | #define CFG_FLASH_READ1 0x0001 /* 1 is standard */ |
| 248 | #define CFG_FLASH_READ2 0x0002 /* 2 is standard */ |
| 249 | |
| 250 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 251 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 252 | #if 0 /* Use NVRAM for environment variables */ |
| 253 | /*----------------------------------------------------------------------- |
| 254 | * NVRAM organization |
| 255 | */ |
| 256 | #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
| 257 | #define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ |
| 258 | #define CFG_ENV_ADDR \ |
| 259 | (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */ |
| 260 | |
| 261 | #else /* Use EEPROM for environment variables */ |
| 262 | |
| 263 | #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
| 264 | #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
| 265 | #define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ |
| 266 | /* total size of a CAT24WC16 is 2048 bytes */ |
| 267 | #endif |
| 268 | |
| 269 | #define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
| 270 | #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ |
| 271 | #define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ |
| 272 | |
| 273 | /*----------------------------------------------------------------------- |
| 274 | * I2C EEPROM (CAT24WC16) for environment |
| 275 | */ |
| 276 | #define CONFIG_HARD_I2C /* I2c with hardware support */ |
| 277 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 278 | #define CFG_I2C_SLAVE 0x7F |
| 279 | |
| 280 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
| 281 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
| 282 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
| 283 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
| 284 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
| 285 | /* 16 byte page write mode using*/ |
| 286 | /* last 4 bits of the address */ |
| 287 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
| 288 | #define CFG_EEPROM_PAGE_WRITE_ENABLE |
| 289 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 290 | /* |
| 291 | * Init Memory Controller: |
| 292 | * |
| 293 | * BR0/1 and OR0/1 (FLASH) |
| 294 | */ |
| 295 | |
| 296 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ |
| 297 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ |
| 298 | |
| 299 | /*----------------------------------------------------------------------- |
| 300 | * External Bus Controller (EBC) Setup |
| 301 | */ |
| 302 | |
| 303 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
| 304 | #define CFG_EBC_PB0AP 0x92015480 |
| 305 | #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
| 306 | |
| 307 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
| 308 | #define CFG_EBC_PB1AP 0x92015480 |
| 309 | #define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ |
| 310 | |
| 311 | /* Memory Bank 2 (CAN0, 1) initialization */ |
| 312 | #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
| 313 | #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
| 314 | #define CFG_LED_ADDR 0xF0000380 |
| 315 | |
| 316 | /* Memory Bank 3 (CompactFlash IDE) initialization */ |
| 317 | #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
| 318 | #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
| 319 | |
| 320 | /* Memory Bank 4 (NVRAM/RTC) initialization */ |
| 321 | /*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ |
| 322 | #define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ |
| 323 | #define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ |
| 324 | |
| 325 | /* Memory Bank 5 (optional Quart) initialization */ |
| 326 | #define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ |
| 327 | #define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ |
| 328 | |
| 329 | /* Memory Bank 6 (FPGA internal) initialization */ |
| 330 | #define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
| 331 | #define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
| 332 | #define CFG_FPGA_BASE_ADDR 0xF0400000 |
| 333 | |
| 334 | /*----------------------------------------------------------------------- |
| 335 | * FPGA stuff |
| 336 | */ |
| 337 | /* FPGA internal regs */ |
| 338 | #define CFG_FPGA_MODE 0x00 |
| 339 | #define CFG_FPGA_STATUS 0x02 |
| 340 | #define CFG_FPGA_TS 0x04 |
| 341 | #define CFG_FPGA_TS_LOW 0x06 |
| 342 | #define CFG_FPGA_TS_CAP0 0x10 |
| 343 | #define CFG_FPGA_TS_CAP0_LOW 0x12 |
| 344 | #define CFG_FPGA_TS_CAP1 0x14 |
| 345 | #define CFG_FPGA_TS_CAP1_LOW 0x16 |
| 346 | #define CFG_FPGA_TS_CAP2 0x18 |
| 347 | #define CFG_FPGA_TS_CAP2_LOW 0x1a |
| 348 | #define CFG_FPGA_TS_CAP3 0x1c |
| 349 | #define CFG_FPGA_TS_CAP3_LOW 0x1e |
| 350 | |
| 351 | /* FPGA Mode Reg */ |
| 352 | #define CFG_FPGA_MODE_CF_RESET 0x0001 |
| 353 | #define CFG_FPGA_MODE_DUART_RESET 0x0002 |
| 354 | #define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ |
| 355 | #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 |
| 356 | #define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 |
| 357 | #define CFG_FPGA_MODE_TS_CLEAR 0x2000 |
| 358 | |
| 359 | /* FPGA Status Reg */ |
| 360 | #define CFG_FPGA_STATUS_DIP0 0x0001 |
| 361 | #define CFG_FPGA_STATUS_DIP1 0x0002 |
| 362 | #define CFG_FPGA_STATUS_DIP2 0x0004 |
| 363 | #define CFG_FPGA_STATUS_FLASH 0x0008 |
| 364 | #define CFG_FPGA_STATUS_TS_IRQ 0x1000 |
| 365 | |
| 366 | #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
| 367 | #define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ |
| 368 | |
| 369 | /* FPGA program pin configuration */ |
| 370 | #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
| 371 | #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ |
| 372 | #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ |
| 373 | #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ |
| 374 | #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ |
| 375 | |
| 376 | /*----------------------------------------------------------------------- |
| 377 | * Definitions for initial stack pointer and data area (in data cache) |
| 378 | */ |
| 379 | #define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ |
| 380 | |
| 381 | #define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
| 382 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
| 383 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| 384 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 385 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 386 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 387 | /* |
| 388 | * Internal Definitions |
| 389 | * |
| 390 | * Boot Flags |
| 391 | */ |
| 392 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 393 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 394 | |
| 395 | #endif /* __CONFIG_H */ |