Heiko Schocher | 23cd0b1 | 2008-01-11 15:15:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <mpc5xxx.h> |
| 26 | #include <pci.h> |
| 27 | |
| 28 | #include "mt48lc16m16a2-75.h" |
| 29 | |
| 30 | #ifndef CFG_RAMBOOT |
| 31 | static void sdram_start (int hi_addr) |
| 32 | { |
| 33 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
| 34 | |
| 35 | /* unlock mode register */ |
| 36 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
| 37 | __asm__ volatile ("sync"); |
| 38 | |
| 39 | /* precharge all banks */ |
| 40 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
| 41 | __asm__ volatile ("sync"); |
| 42 | |
| 43 | #if SDRAM_DDR |
| 44 | /* set mode register: extended mode */ |
| 45 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
| 46 | __asm__ volatile ("sync"); |
| 47 | |
| 48 | /* set mode register: reset DLL */ |
| 49 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
| 50 | __asm__ volatile ("sync"); |
| 51 | #endif |
| 52 | |
| 53 | /* precharge all banks */ |
| 54 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
| 55 | __asm__ volatile ("sync"); |
| 56 | |
| 57 | /* auto refresh */ |
| 58 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
| 59 | __asm__ volatile ("sync"); |
| 60 | |
| 61 | /* set mode register */ |
| 62 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
| 63 | __asm__ volatile ("sync"); |
| 64 | |
| 65 | /* normal operation */ |
| 66 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
| 67 | __asm__ volatile ("sync"); |
| 68 | } |
| 69 | #endif |
| 70 | |
| 71 | /* |
| 72 | * ATTENTION: Although partially referenced initdram does NOT make real use |
| 73 | * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE |
| 74 | * is something else than 0x00000000. |
| 75 | */ |
| 76 | |
Becky Bruce | bd99ae7 | 2008-06-09 16:03:40 -0500 | [diff] [blame] | 77 | phys_size_t initdram (int board_type) |
Heiko Schocher | 23cd0b1 | 2008-01-11 15:15:14 +0100 | [diff] [blame] | 78 | { |
| 79 | ulong dramsize = 0; |
| 80 | ulong dramsize2 = 0; |
| 81 | #ifndef CFG_RAMBOOT |
| 82 | ulong test1, test2; |
| 83 | |
| 84 | /* setup SDRAM chip selects */ |
| 85 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */ |
| 86 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */ |
| 87 | __asm__ volatile ("sync"); |
| 88 | |
| 89 | /* setup config registers */ |
| 90 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
| 91 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
| 92 | __asm__ volatile ("sync"); |
| 93 | |
| 94 | #if SDRAM_DDR && SDRAM_TAPDELAY |
| 95 | /* set tap delay */ |
| 96 | *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; |
| 97 | __asm__ volatile ("sync"); |
| 98 | #endif |
| 99 | |
| 100 | /* find RAM size using SDRAM CS0 only */ |
| 101 | sdram_start(0); |
| 102 | test1 = (ulong )get_ram_size((long *)CFG_SDRAM_BASE, 0x10000000); |
| 103 | sdram_start(1); |
| 104 | test2 = (ulong )get_ram_size((long *)CFG_SDRAM_BASE, 0x10000000); |
| 105 | if (test1 > test2) { |
| 106 | sdram_start(0); |
| 107 | dramsize = test1; |
| 108 | } else { |
| 109 | dramsize = test2; |
| 110 | } |
| 111 | |
| 112 | /* memory smaller than 1MB is impossible */ |
| 113 | if (dramsize < (1 << 20)) { |
| 114 | dramsize = 0; |
| 115 | } |
| 116 | |
| 117 | /* set SDRAM CS0 size according to the amount of RAM found */ |
| 118 | if (dramsize > 0) { |
| 119 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; |
| 120 | } else { |
| 121 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
| 122 | } |
| 123 | |
| 124 | #else /* CFG_RAMBOOT */ |
| 125 | |
| 126 | /* retrieve size of memory connected to SDRAM CS0 */ |
| 127 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; |
| 128 | if (dramsize >= 0x13) { |
| 129 | dramsize = (1 << (dramsize - 0x13)) << 20; |
| 130 | } else { |
| 131 | dramsize = 0; |
| 132 | } |
| 133 | |
| 134 | /* retrieve size of memory connected to SDRAM CS1 */ |
| 135 | dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; |
| 136 | if (dramsize2 >= 0x13) { |
| 137 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; |
| 138 | } else { |
| 139 | dramsize2 = 0; |
| 140 | } |
| 141 | |
| 142 | #endif /* CFG_RAMBOOT */ |
| 143 | |
| 144 | return dramsize + dramsize2; |
| 145 | } |
| 146 | |
| 147 | int checkboard (void) |
| 148 | { |
| 149 | puts ("Board: MUNICes\n"); |
| 150 | return 0; |
| 151 | } |
| 152 | |
| 153 | #ifdef CONFIG_PCI |
| 154 | static struct pci_controller hose; |
| 155 | |
| 156 | extern void pci_mpc5xxx_init(struct pci_controller *); |
| 157 | |
| 158 | void pci_init_board(void) |
| 159 | { |
| 160 | pci_mpc5xxx_init(&hose); |
| 161 | } |
| 162 | #endif |
| 163 | |
| 164 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
| 165 | void |
| 166 | ft_board_setup(void *blob, bd_t *bd) |
| 167 | { |
| 168 | ft_cpu_setup(blob, bd); |
| 169 | } |
| 170 | #endif |