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Marian Balakowiczc9b21e62006-03-14 15:59:25 +01001/*
2 * (C) Copyright 2001, 2002, 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com`
5 * Steven Scholz, steven.scholz@imc-berlin.de
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Marian Balakowiczc9b21e62006-03-14 15:59:25 +01008 */
9
10/*
11 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
12 * DS1374 Real Time Clock (RTC).
13 *
14 * based on ds1337.c
15 */
16
17#include <common.h>
18#include <command.h>
19#include <rtc.h>
20#include <i2c.h>
21
Michal Simekc3e6c552008-07-14 19:45:37 +020022#if defined(CONFIG_CMD_DATE)
Marian Balakowiczc9b21e62006-03-14 15:59:25 +010023
24/*---------------------------------------------------------------------*/
25#undef DEBUG_RTC
26#define DEBUG_RTC
27
28#ifdef DEBUG_RTC
29#define DEBUGR(fmt,args...) printf(fmt ,##args)
30#else
31#define DEBUGR(fmt,args...)
32#endif
33/*---------------------------------------------------------------------*/
34
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035#ifndef CONFIG_SYS_I2C_RTC_ADDR
36# define CONFIG_SYS_I2C_RTC_ADDR 0x68
Marian Balakowiczc9b21e62006-03-14 15:59:25 +010037#endif
38
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039#if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
Marian Balakowiczc9b21e62006-03-14 15:59:25 +010040# error The DS1374 is specified up to 400kHz in fast mode!
41#endif
42
43/*
44 * RTC register addresses
45 */
46#define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */
47#define RTC_TOD_CNT_BYTE1_ADDR 0x01
48#define RTC_TOD_CNT_BYTE2_ADDR 0x02
49#define RTC_TOD_CNT_BYTE3_ADDR 0x03
50
51#define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04
52#define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05
53#define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06
54
55#define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */
56#define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */
57#define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
58
59#define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */
60#define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */
61#define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */
62#define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */
63#define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */
64#define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */
65#define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
66#define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */
67
68#define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */
69#define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */
70
Marian Balakowiczc9b21e62006-03-14 15:59:25 +010071const char RtcTodAddr[] = {
72 RTC_TOD_CNT_BYTE0_ADDR,
73 RTC_TOD_CNT_BYTE1_ADDR,
74 RTC_TOD_CNT_BYTE2_ADDR,
75 RTC_TOD_CNT_BYTE3_ADDR
76};
77
78static uchar rtc_read (uchar reg);
York Sun4a598092013-04-01 11:29:11 -070079static void rtc_write(uchar reg, uchar val, bool set);
Marian Balakowiczc9b21e62006-03-14 15:59:25 +010080static void rtc_write_raw (uchar reg, uchar val);
81
82/*
83 * Get the current time from the RTC
84 */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030085int rtc_get (struct rtc_time *tm){
86 int rel = 0;
Marian Balakowiczc9b21e62006-03-14 15:59:25 +010087 unsigned long time1, time2;
88 unsigned int limit;
89 unsigned char tmp;
90 unsigned int i;
91
92 /*
93 * Since the reads are being performed one byte at a time,
Wolfgang Denkebd3deb2006-04-16 10:51:58 +020094 * there is a chance that a carry will occur during the read.
Marian Balakowiczc9b21e62006-03-14 15:59:25 +010095 * To detect this, 2 reads are performed and compared.
96 */
97 limit = 10;
98 do {
99 i = 4;
100 time1 = 0;
101 while (i--) {
102 tmp = rtc_read(RtcTodAddr[i]);
103 time1 = (time1 << 8) | (tmp & 0xff);
104 }
105
106 i = 4;
107 time2 = 0;
108 while (i--) {
109 tmp = rtc_read(RtcTodAddr[i]);
110 time2 = (time2 << 8) | (tmp & 0xff);
111 }
112 } while ((time1 != time2) && limit--);
113
114 if (time1 != time2) {
115 printf("can't get consistent time from rtc chip\n");
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300116 rel = -1;
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100117 }
118
Kim Phillipsf91aa8d2008-07-10 14:00:15 -0500119 DEBUGR ("Get RTC s since 1.1.1970: %ld\n", time1);
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100120
121 to_tm(time1, tm); /* To Gregorian Date */
122
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300123 if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) {
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100124 printf ("### Warning: RTC oscillator has stopped\n");
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300125 rel = -1;
126 }
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100127
128 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
129 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
130 tm->tm_hour, tm->tm_min, tm->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300131
132 return rel;
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100133}
134
135/*
136 * Set the RTC
137 */
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200138int rtc_set (struct rtc_time *tmp){
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100139
140 unsigned long time;
141 unsigned i;
142
143 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
144 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
145 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
146
147 if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
148 printf("WARNING: year should be between 1970 and 2069!\n");
149
150 time = mktime(tmp->tm_year, tmp->tm_mon,
151 tmp->tm_mday, tmp->tm_hour,
152 tmp->tm_min, tmp->tm_sec);
153
Kim Phillipsf91aa8d2008-07-10 14:00:15 -0500154 DEBUGR ("Set RTC s since 1.1.1970: %ld (0x%02lx)\n", time, time);
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100155
156 /* write to RTC_TOD_CNT_BYTEn_ADDR */
157 for (i = 0; i <= 3; i++) {
158 rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff));
159 time = time >> 8;
160 }
161
162 /* Start clock */
York Sun4a598092013-04-01 11:29:11 -0700163 rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, false);
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200164
165 return 0;
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100166}
167
168/*
169 * Reset the RTC. We setting the date back to 1970-01-01.
170 * We also enable the oscillator output on the SQW/OUT pin and program
171 * it for 32,768 Hz output. Note that according to the datasheet, turning
172 * on the square wave output increases the current drain on the backup
173 * battery to something between 480nA and 800nA.
174 */
175void rtc_reset (void){
176
177 struct rtc_time tmp;
178
179 /* clear status flags */
York Sun4a598092013-04-01 11:29:11 -0700180 rtc_write(RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), false); /* clearing OSF and AF */
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100181
182 /* Initialise DS1374 oriented to MPC8349E-ADS */
183 rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
184 |RTC_CTL_BIT_WACE
York Sun4a598092013-04-01 11:29:11 -0700185 |RTC_CTL_BIT_AIE), false);/* start osc, disable WACE, clear AIE
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100186 - set to 0 */
187 rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
188 |RTC_CTL_BIT_WDSTR
189 |RTC_CTL_BIT_RS1
190 |RTC_CTL_BIT_RS2
York Sun4a598092013-04-01 11:29:11 -0700191 |RTC_CTL_BIT_BBSQW), true);/* disable WD/ALM, WDSTR set to INT-pin,
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100192 set BBSQW and SQW to 32k
193 - set to 1 */
194 tmp.tm_year = 1970;
195 tmp.tm_mon = 1;
196 tmp.tm_mday= 1;
197 tmp.tm_hour = 0;
198 tmp.tm_min = 0;
199 tmp.tm_sec = 0;
200
201 rtc_set(&tmp);
202
203 printf("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
204 tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
205 tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
206
York Sun4a598092013-04-01 11:29:11 -0700207 rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAC, true);
208 rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR, 0xDE, true);
209 rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAD, true);
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100210}
211
212/*
213 * Helper functions
214 */
215static uchar rtc_read (uchar reg)
216{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100218}
219
York Sun4a598092013-04-01 11:29:11 -0700220static void rtc_write(uchar reg, uchar val, bool set)
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100221{
York Sun4a598092013-04-01 11:29:11 -0700222 if (set == true) {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223 val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg);
224 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100225 } else {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226 val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val;
227 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100228 }
229}
230
231static void rtc_write_raw (uchar reg, uchar val)
232{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
Marian Balakowiczc9b21e62006-03-14 15:59:25 +0100234}
Jon Loeliger07efe2a2007-07-10 10:27:39 -0500235#endif