Cyril Chemparathy | 692a7af | 2010-06-07 14:13:32 -0400 | [diff] [blame] | 1 | /* |
| 2 | * TNETV107X: Clock APIs |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 20 | */ |
| 21 | |
| 22 | #ifndef __ASM_ARCH_CLOCK_H |
| 23 | #define __ASM_ARCH_CLOCK_H |
| 24 | |
| 25 | #define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0 |
| 26 | #define PSC_MDCTL_NEXT_SYNCRST 0x1 |
| 27 | #define PSC_MDCTL_NEXT_DISABLE 0x2 |
| 28 | #define PSC_MDCTL_NEXT_ENABLE 0x3 |
| 29 | |
| 30 | #define CONFIG_SYS_INT_OSC_FREQ 24000000 |
| 31 | |
| 32 | #ifndef __ASSEMBLY__ |
| 33 | |
| 34 | /* PLL identifiers */ |
| 35 | enum pll_type_e { |
| 36 | SYS_PLL, |
| 37 | TDM_PLL, |
| 38 | ETH_PLL |
| 39 | }; |
| 40 | |
| 41 | /* PLL configuration data */ |
| 42 | struct pll_init_data { |
| 43 | int pll; |
| 44 | int internal_osc; |
| 45 | unsigned long pll_freq; |
| 46 | unsigned long div_freq[10]; |
| 47 | }; |
| 48 | |
| 49 | void init_plls(int num_pll, struct pll_init_data *config); |
| 50 | int lpsc_status(unsigned int mod); |
| 51 | void lpsc_control(int mod, unsigned long state, int lrstz); |
| 52 | unsigned long clk_get_rate(unsigned int clk); |
| 53 | unsigned long clk_round_rate(unsigned int clk, unsigned long hz); |
| 54 | int clk_set_rate(unsigned int clk, unsigned long hz); |
| 55 | |
| 56 | static inline void clk_enable(unsigned int mod) |
| 57 | { |
| 58 | lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1); |
| 59 | } |
| 60 | |
| 61 | static inline void clk_disable(unsigned int mod) |
| 62 | { |
| 63 | lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1); |
| 64 | } |
| 65 | |
| 66 | #endif |
| 67 | |
| 68 | #endif |