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git01.mediatek.com / filogic / uboot / 4d81b2de31a87d9d55e5285a103093fd3344bac2 / . / arch / arm / include / asm / arch-davinci / ddr2_defs.h
blob: 4f943b81b36d4a7b1f46c3bfaf60a67d36600151 [file] [log] [blame]
Heiko Schochera25f3d02011-09-14 19:59:36 +0000[diff] [blame]1/*
2 * Copyright (C) 2011
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23#ifndef _DV_DDR2_DEFS_H_
24#define _DV_DDR2_DEFS_H_
25
26/*
27 * DDR2 Memory Ctrl Register structure
28 * See sprueh7d.pdf for more details.
29 */
30struct dv_ddr2_regs_ctrl {
31 unsigned char rsvd0[4]; /* 0x00 */
32 unsigned int sdrstat; /* 0x04 */
33 unsigned int sdbcr; /* 0x08 */
34 unsigned int sdrcr; /* 0x0C */
35 unsigned int sdtimr; /* 0x10 */
36 unsigned int sdtimr2; /* 0x14 */
37 unsigned char rsvd1[4]; /* 0x18 */
38 unsigned int sdbcr2; /* 0x1C */
39 unsigned int pbbpr; /* 0x20 */
40 unsigned char rsvd2[156]; /* 0x24 */
41 unsigned int irr; /* 0xC0 */
42 unsigned int imr; /* 0xC4 */
43 unsigned int imsr; /* 0xC8 */
44 unsigned int imcr; /* 0xCC */
45 unsigned char rsvd3[20]; /* 0xD0 */
46 unsigned int ddrphycr; /* 0xE4 */
47 unsigned int ddrphycr2; /* 0xE8 */
48 unsigned char rsvd4[4]; /* 0xEC */
49};
50
51#define DV_DDR_PHY_PWRDNEN 0x40
52#define DV_DDR_PHY_EXT_STRBEN 0x80
53#define DV_DDR_PHY_RD_LATENCY_SHIFT 0
54
55#define DV_DDR_SDTMR1_RFC_SHIFT 25
56#define DV_DDR_SDTMR1_RP_SHIFT 22
57#define DV_DDR_SDTMR1_RCD_SHIFT 19
58#define DV_DDR_SDTMR1_WR_SHIFT 16
59#define DV_DDR_SDTMR1_RAS_SHIFT 11
60#define DV_DDR_SDTMR1_RC_SHIFT 6
61#define DV_DDR_SDTMR1_RRD_SHIFT 3
62#define DV_DDR_SDTMR1_WTR_SHIFT 0
63
64#define DV_DDR_SDTMR2_RASMAX_SHIFT 27
65#define DV_DDR_SDTMR2_XP_SHIFT 25
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]66#define DV_DDR_SDTMR2_ODT_SHIFT 23
Heiko Schochera25f3d02011-09-14 19:59:36 +0000[diff] [blame]67#define DV_DDR_SDTMR2_XSNR_SHIFT 16
68#define DV_DDR_SDTMR2_XSRD_SHIFT 8
69#define DV_DDR_SDTMR2_RTP_SHIFT 5
70#define DV_DDR_SDTMR2_CKE_SHIFT 0
71
72#define DV_DDR_SDCR_DDR2TERM1_SHIFT 27
73#define DV_DDR_SDCR_IBANK_POS_SHIFT 26
74#define DV_DDR_SDCR_MSDRAMEN_SHIFT 25
75#define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24
76#define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23
77#define DV_DDR_SDCR_DDR_DDQS_SHIFT 22
78#define DV_DDR_SDCR_DDR2EN_SHIFT 20
79#define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18
80#define DV_DDR_SDCR_DDREN_SHIFT 17
81#define DV_DDR_SDCR_SDRAMEN_SHIFT 16
82#define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15
83#define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14
84#define DV_DDR_SDCR_CL_SHIFT 9
85#define DV_DDR_SDCR_IBANK_SHIFT 4
86#define DV_DDR_SDCR_PAGESIZE_SHIFT 0
87
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]88#define DV_DDR_SDRCR_LPMODEN (1 << 31)
89#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30)
90
Heiko Schochera25f3d02011-09-14 19:59:36 +0000[diff] [blame]91#define DV_DDR_SRCR_LPMODEN_SHIFT 31
92#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30
93
94#define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT)
95#define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)
96
97#define dv_ddr2_regs_ctrl \
98 ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
99
100#endif /* _DV_DDR2_DEFS_H_ */