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git01.mediatek.com / filogic / uboot / 4d7cbe5032572a02a01938b2f3d10f53abdb75b7 / . / include / configs / ls1012aqds.h
blob: 9498a03f405b0af745e2953c01cc8d26d4bf7dec [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]2/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]4 */
5
6#ifndef __LS1012AQDS_H__
7#define __LS1012AQDS_H__
8
9#include "ls1012a_common.h"
10
Shengzhou Liucb7fb122016-08-26 18:30:39 +0800[diff] [blame]11/* DDR */
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]12#define CONFIG_DIMM_SLOTS_PER_CTLR 1
13#define CONFIG_CHIP_SELECTS_PER_CTRL 1
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]14#define CONFIG_SYS_SDRAM_SIZE 0x40000000
Shengzhou Liucb7fb122016-08-26 18:30:39 +0800[diff] [blame]15
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]16/*
17 * QIXIS Definitions
18 */
19#define CONFIG_FSL_QIXIS
20
21#ifdef CONFIG_FSL_QIXIS
22#define CONFIG_QIXIS_I2C_ACCESS
23#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
24#define QIXIS_LBMAP_BRDCFG_REG 0x04
25#define QIXIS_LBMAP_SWITCH 6
Prabhakar Kushwaha66481272016-07-19 14:05:47 +0530[diff] [blame]26#define QIXIS_LBMAP_MASK 0x08
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]27#define QIXIS_LBMAP_SHIFT 0
28#define QIXIS_LBMAP_DFLTBANK 0x00
29#define QIXIS_LBMAP_ALTBANK 0x08
Prabhakar Kushwaha66481272016-07-19 14:05:47 +0530[diff] [blame]30#define QIXIS_RST_CTL_RESET 0x31
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]31#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
32#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
33#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
34#endif
35
36/*
37 * I2C bus multiplexer
38 */
39#define I2C_MUX_PCA_ADDR_PRI 0x77
40#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
41#define I2C_RETIMER_ADDR 0x18
42#define I2C_MUX_CH_DEFAULT 0x8
43#define I2C_MUX_CH_CH7301 0xC
44#define I2C_MUX_CH5 0xD
45#define I2C_MUX_CH7 0xF
46
47#define I2C_MUX_CH_VOL_MONITOR 0xa
48
49/*
50* RTC configuration
51*/
52#define RTC
53#define CONFIG_RTC_PCF8563 1
54#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]55
56/* EEPROM */
57#define CONFIG_ID_EEPROM
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]58#define CONFIG_SYS_I2C_EEPROM_NXID
59#define CONFIG_SYS_EEPROM_BUS_NUM 0
60#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
61#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
62#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
63#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
64
65
66/* Voltage monitor on channel 2*/
67#define I2C_VOL_MONITOR_ADDR 0x40
68#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
69#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
70#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
71
72/* DSPI */
73#define CONFIG_FSL_DSPI1
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]74
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]75#define MMAP_DSPI DSPI1_BASE_ADDR
76
77#define CONFIG_SYS_DSPI_CTAR0 1
78
79#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
80 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
81 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
82 DSPI_CTAR_DT(0))
83#define CONFIG_SPI_FLASH_SST /* cs1 */
84
85#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
86 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
87 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
88 DSPI_CTAR_DT(0))
89#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
90
91#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
92 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
93 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
94 DSPI_CTAR_DT(0))
95#define CONFIG_SPI_FLASH_EON /* cs3 */
96
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]97/* MMC */
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]98#ifdef CONFIG_MMC
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]99#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]100#endif
101
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]102#define CONFIG_PCIE1 /* PCIE controller 1 */
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]103
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]104#define CONFIG_PCI_SCAN_SHOW
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]105
Rajesh Bhagatbf39fe62018-11-05 18:02:59 +0000[diff] [blame]106#include <asm/fsl_secure_boot.h>
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]107#endif /* __LS1012AQDS_H__ */