blob: 491893a17dc45e2cc5584efd9c1b6178d41bf5d0 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glassb2c1cac2014-02-26 15:59:21 -07006/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060010 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070011
Simon Glassfef72b72014-07-23 06:55:03 -060012 aliases {
13 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060014 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070015 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060016 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060017 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010019 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070020 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060021 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070023 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070025 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020026 remoteproc0 = &rproc_1;
27 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060028 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060030 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020031 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070032 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020038 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060042 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020045 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020046 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060047 };
48
Simon Glassed96cde2018-12-10 10:37:33 -070049 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Philippe Reynes1ee26482020-07-24 18:19:51 +020054 buttons {
55 compatible = "gpio-keys";
56
57 summer {
58 gpios = <&gpio_a 3 0>;
59 label = "summer";
60 };
61
62 christmas {
63 gpios = <&gpio_a 4 0>;
64 label = "christmas";
65 };
66 };
67
Simon Glassc953aaf2018-12-10 10:37:34 -070068 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060069 reg = <0 0>;
70 compatible = "google,cros-ec-sandbox";
71
72 /*
73 * This describes the flash memory within the EC. Note
74 * that the STM32L flash erases to 0, not 0xff.
75 */
76 flash {
77 image-pos = <0x08000000>;
78 size = <0x20000>;
79 erase-value = <0>;
80
81 /* Information for sandbox */
82 ro {
83 image-pos = <0>;
84 size = <0xf000>;
85 };
86 wp-ro {
87 image-pos = <0xf000>;
88 size = <0x1000>;
89 };
90 rw {
91 image-pos = <0x10000>;
92 size = <0x10000>;
93 };
94 };
95 };
96
Yannick Fertré9712c822019-10-07 15:29:05 +020097 dsi_host: dsi_host {
98 compatible = "sandbox,dsi-host";
99 };
100
Simon Glassb2c1cac2014-02-26 15:59:21 -0700101 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600102 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700103 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600104 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700105 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600106 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100107 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
108 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700109 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100110 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
111 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
112 <&gpio_b 7 GPIO_IN 3 2 1>,
113 <&gpio_b 8 GPIO_OUT 3 2 1>,
114 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100115 test3-gpios =
116 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
117 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
118 <&gpio_c 2 GPIO_OUT>,
119 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
120 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200121 <&gpio_c 5 GPIO_IN>,
122 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
123 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Simon Glass6df01f92018-12-10 10:37:37 -0700124 int-value = <1234>;
125 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200126 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200127 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600128 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700129 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600130 acpi,name = "GHIJ";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700131 };
132
133 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600134 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700135 compatible = "not,compatible";
136 };
137
138 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600139 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700140 };
141
Simon Glass5620cf82018-10-01 12:22:40 -0600142 backlight: backlight {
143 compatible = "pwm-backlight";
144 enable-gpios = <&gpio_a 1>;
145 power-supply = <&ldo_1>;
146 pwms = <&pwm 0 1000>;
147 default-brightness-level = <5>;
148 brightness-levels = <0 16 32 64 128 170 202 234 255>;
149 };
150
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200151 bind-test {
152 bind-test-child1 {
153 compatible = "sandbox,phy";
154 #phy-cells = <1>;
155 };
156
157 bind-test-child2 {
158 compatible = "simple-bus";
159 };
160 };
161
Simon Glassb2c1cac2014-02-26 15:59:21 -0700162 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600163 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700164 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600165 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700166 ping-add = <3>;
167 };
168
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200169 phy_provider0: gen_phy@0 {
170 compatible = "sandbox,phy";
171 #phy-cells = <1>;
172 };
173
174 phy_provider1: gen_phy@1 {
175 compatible = "sandbox,phy";
176 #phy-cells = <0>;
177 broken;
178 };
179
developer71092972020-05-02 11:35:12 +0200180 phy_provider2: gen_phy@2 {
181 compatible = "sandbox,phy";
182 #phy-cells = <0>;
183 };
184
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200185 gen_phy_user: gen_phy_user {
186 compatible = "simple-bus";
187 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
188 phy-names = "phy1", "phy2", "phy3";
189 };
190
developer71092972020-05-02 11:35:12 +0200191 gen_phy_user1: gen_phy_user1 {
192 compatible = "simple-bus";
193 phys = <&phy_provider0 0>, <&phy_provider2>;
194 phy-names = "phy1", "phy2";
195 };
196
Simon Glassb2c1cac2014-02-26 15:59:21 -0700197 some-bus {
198 #address-cells = <1>;
199 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600200 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600201 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600202 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700203 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600204 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700205 compatible = "denx,u-boot-fdt-test";
206 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600207 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700208 ping-add = <5>;
209 };
Simon Glass40717422014-07-23 06:55:18 -0600210 c-test@0 {
211 compatible = "denx,u-boot-fdt-test";
212 reg = <0>;
213 ping-expect = <6>;
214 ping-add = <6>;
215 };
216 c-test@1 {
217 compatible = "denx,u-boot-fdt-test";
218 reg = <1>;
219 ping-expect = <7>;
220 ping-add = <7>;
221 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700222 };
223
224 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600225 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600226 ping-expect = <6>;
227 ping-add = <6>;
228 compatible = "google,another-fdt-test";
229 };
230
231 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600232 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600233 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700234 ping-add = <6>;
235 compatible = "google,another-fdt-test";
236 };
237
Simon Glass0ccb0972015-01-25 08:27:05 -0700238 f-test {
239 compatible = "denx,u-boot-fdt-test";
240 };
241
242 g-test {
243 compatible = "denx,u-boot-fdt-test";
244 };
245
Bin Mengd9d24782018-10-10 22:07:01 -0700246 h-test {
247 compatible = "denx,u-boot-fdt-test1";
248 };
249
developercf8bc132020-05-02 11:35:10 +0200250 i-test {
251 compatible = "mediatek,u-boot-fdt-test";
252 #address-cells = <1>;
253 #size-cells = <0>;
254
255 subnode@0 {
256 reg = <0>;
257 };
258
259 subnode@1 {
260 reg = <1>;
261 };
262
263 subnode@2 {
264 reg = <2>;
265 };
266 };
267
Simon Glass204675c2019-12-29 21:19:25 -0700268 devres-test {
269 compatible = "denx,u-boot-devres-test";
270 };
271
Simon Glass3c601b12020-07-07 13:12:06 -0600272 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600273 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600274 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600275 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600276 child {
277 compatible = "denx,u-boot-acpi-test";
278 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600279 };
280
Simon Glass3c601b12020-07-07 13:12:06 -0600281 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600282 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600283 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600284 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600285 };
286
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200287 clocks {
288 clk_fixed: clk-fixed {
289 compatible = "fixed-clock";
290 #clock-cells = <0>;
291 clock-frequency = <1234>;
292 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000293
294 clk_fixed_factor: clk-fixed-factor {
295 compatible = "fixed-factor-clock";
296 #clock-cells = <0>;
297 clock-div = <3>;
298 clock-mult = <2>;
299 clocks = <&clk_fixed>;
300 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200301
302 osc {
303 compatible = "fixed-clock";
304 #clock-cells = <0>;
305 clock-frequency = <20000000>;
306 };
Stephen Warrena9622432016-06-17 09:44:00 -0600307 };
308
309 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600310 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600311 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200312 assigned-clocks = <&clk_sandbox 3>;
313 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600314 };
315
316 clk-test {
317 compatible = "sandbox,clk-test";
318 clocks = <&clk_fixed>,
319 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200320 <&clk_sandbox 0>,
321 <&clk_sandbox 3>,
322 <&clk_sandbox 2>;
323 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600324 };
325
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200326 ccf: clk-ccf {
327 compatible = "sandbox,clk-ccf";
328 };
329
Simon Glass5b968632015-05-22 15:42:15 -0600330 eth@10002000 {
331 compatible = "sandbox,eth";
332 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500333 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600334 };
335
336 eth_5: eth@10003000 {
337 compatible = "sandbox,eth";
338 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500339 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600340 };
341
Bin Meng04a11cb2015-08-27 22:25:53 -0700342 eth_3: sbe5 {
343 compatible = "sandbox,eth";
344 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500345 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700346 };
347
Simon Glass5b968632015-05-22 15:42:15 -0600348 eth@10004000 {
349 compatible = "sandbox,eth";
350 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500351 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600352 };
353
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700354 firmware {
355 sandbox_firmware: sandbox-firmware {
356 compatible = "sandbox,firmware";
357 };
358 };
359
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100360 pinctrl-gpio {
361 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700362
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100363 gpio_a: base-gpios {
364 compatible = "sandbox,gpio";
365 gpio-controller;
366 #gpio-cells = <1>;
367 gpio-bank-name = "a";
368 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200369 hog_input_active_low {
370 gpio-hog;
371 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200372 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200373 };
374 hog_input_active_high {
375 gpio-hog;
376 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200377 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200378 };
379 hog_output_low {
380 gpio-hog;
381 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200382 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200383 };
384 hog_output_high {
385 gpio-hog;
386 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200387 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200388 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100389 };
390
391 gpio_b: extra-gpios {
392 compatible = "sandbox,gpio";
393 gpio-controller;
394 #gpio-cells = <5>;
395 gpio-bank-name = "b";
396 sandbox,gpio-count = <10>;
397 };
Simon Glass25348a42014-10-13 23:42:11 -0600398
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100399 gpio_c: pinmux-gpios {
400 compatible = "sandbox,gpio";
401 gpio-controller;
402 #gpio-cells = <2>;
403 gpio-bank-name = "c";
404 sandbox,gpio-count = <10>;
405 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100406 };
407
Simon Glass7df766e2014-12-10 08:55:55 -0700408 i2c@0 {
409 #address-cells = <1>;
410 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600411 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700412 compatible = "sandbox,i2c";
413 clock-frequency = <100000>;
414 eeprom@2c {
415 reg = <0x2c>;
416 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700417 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700418 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200419
Simon Glass336b2952015-05-22 15:42:17 -0600420 rtc_0: rtc@43 {
421 reg = <0x43>;
422 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700423 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600424 };
425
426 rtc_1: rtc@61 {
427 reg = <0x61>;
428 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700429 sandbox,emul = <&emul1>;
430 };
431
432 i2c_emul: emul {
433 reg = <0xff>;
434 compatible = "sandbox,i2c-emul-parent";
435 emul_eeprom: emul-eeprom {
436 compatible = "sandbox,i2c-eeprom";
437 sandbox,filename = "i2c.bin";
438 sandbox,size = <256>;
439 };
440 emul0: emul0 {
441 compatible = "sandbox,i2c-rtc";
442 };
443 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600444 compatible = "sandbox,i2c-rtc";
445 };
446 };
447
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200448 sandbox_pmic: sandbox_pmic {
449 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700450 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200451 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200452
453 mc34708: pmic@41 {
454 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700455 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200456 };
Simon Glass7df766e2014-12-10 08:55:55 -0700457 };
458
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100459 bootcount@0 {
460 compatible = "u-boot,bootcount-rtc";
461 rtc = <&rtc_1>;
462 offset = <0x13>;
463 };
464
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100465 adc@0 {
466 compatible = "sandbox,adc";
467 vdd-supply = <&buck2>;
468 vss-microvolts = <0>;
469 };
470
Simon Glass515dcff2020-02-06 09:55:00 -0700471 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700472 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700473 interrupt-controller;
474 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700475 };
476
Simon Glass90b6fef2016-01-18 19:52:26 -0700477 lcd {
478 u-boot,dm-pre-reloc;
479 compatible = "sandbox,lcd-sdl";
480 xres = <1366>;
481 yres = <768>;
482 };
483
Simon Glassd783eb32015-07-06 12:54:34 -0600484 leds {
485 compatible = "gpio-leds";
486
487 iracibble {
488 gpios = <&gpio_a 1 0>;
489 label = "sandbox:red";
490 };
491
492 martinet {
493 gpios = <&gpio_a 2 0>;
494 label = "sandbox:green";
495 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200496
497 default_on {
498 gpios = <&gpio_a 5 0>;
499 label = "sandbox:default_on";
500 default-state = "on";
501 };
502
503 default_off {
504 gpios = <&gpio_a 6 0>;
505 label = "sandbox:default_off";
506 default-state = "off";
507 };
Simon Glassd783eb32015-07-06 12:54:34 -0600508 };
509
Stephen Warren62f2c902016-05-16 17:41:37 -0600510 mbox: mbox {
511 compatible = "sandbox,mbox";
512 #mbox-cells = <1>;
513 };
514
515 mbox-test {
516 compatible = "sandbox,mbox-test";
517 mboxes = <&mbox 100>, <&mbox 1>;
518 mbox-names = "other", "test";
519 };
520
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900521 cpus {
522 cpu-test1 {
523 compatible = "sandbox,cpu_sandbox";
524 u-boot,dm-pre-reloc;
525 };
Mario Sixdea5df72018-08-06 10:23:44 +0200526
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900527 cpu-test2 {
528 compatible = "sandbox,cpu_sandbox";
529 u-boot,dm-pre-reloc;
530 };
Mario Sixdea5df72018-08-06 10:23:44 +0200531
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900532 cpu-test3 {
533 compatible = "sandbox,cpu_sandbox";
534 u-boot,dm-pre-reloc;
535 };
Mario Sixdea5df72018-08-06 10:23:44 +0200536 };
537
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500538 chipid: chipid {
539 compatible = "sandbox,soc";
540 };
541
Simon Glassc953aaf2018-12-10 10:37:34 -0700542 i2s: i2s {
543 compatible = "sandbox,i2s";
544 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700545 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700546 };
547
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200548 nop-test_0 {
549 compatible = "sandbox,nop_sandbox1";
550 nop-test_1 {
551 compatible = "sandbox,nop_sandbox2";
552 bind = "True";
553 };
554 nop-test_2 {
555 compatible = "sandbox,nop_sandbox2";
556 bind = "False";
557 };
558 };
559
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200560 misc-test {
561 compatible = "sandbox,misc_sandbox";
562 };
563
Simon Glasse4fef742017-04-23 20:02:07 -0600564 mmc2 {
565 compatible = "sandbox,mmc";
566 };
567
568 mmc1 {
569 compatible = "sandbox,mmc";
570 };
571
572 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600573 compatible = "sandbox,mmc";
574 };
575
Simon Glass53a68b32019-02-16 20:24:50 -0700576 pch {
577 compatible = "sandbox,pch";
578 };
579
Tom Rini4a3ca482020-02-11 12:41:23 -0500580 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700581 compatible = "sandbox,pci";
582 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500583 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700584 #address-cells = <3>;
585 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600586 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700587 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700588 pci@0,0 {
589 compatible = "pci-generic";
590 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600591 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700592 };
Alex Margineanf1274432019-06-07 11:24:24 +0300593 pci@1,0 {
594 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600595 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
596 reg = <0x02000814 0 0 0 0
597 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600598 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300599 };
Simon Glass937bb472019-12-06 21:41:57 -0700600 p2sb-pci@2,0 {
601 compatible = "sandbox,p2sb";
602 reg = <0x02001010 0 0 0 0>;
603 sandbox,emul = <&p2sb_emul>;
604
605 adder {
606 intel,p2sb-port-id = <3>;
607 compatible = "sandbox,adder";
608 };
609 };
Simon Glass8c501022019-12-06 21:41:54 -0700610 pci@1e,0 {
611 compatible = "sandbox,pmc";
612 reg = <0xf000 0 0 0 0>;
613 sandbox,emul = <&pmc_emul1e>;
614 acpi-base = <0x400>;
615 gpe0-dwx-mask = <0xf>;
616 gpe0-dwx-shift-base = <4>;
617 gpe0-dw = <6 7 9>;
618 gpe0-sts = <0x20>;
619 gpe0-en = <0x30>;
620 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700621 pci@1f,0 {
622 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600623 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
624 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600625 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700626 };
627 };
628
Simon Glassb98ba4c2019-09-25 08:56:10 -0600629 pci-emul0 {
630 compatible = "sandbox,pci-emul-parent";
631 swap_case_emul0_0: emul0@0,0 {
632 compatible = "sandbox,swap-case";
633 };
634 swap_case_emul0_1: emul0@1,0 {
635 compatible = "sandbox,swap-case";
636 use-ea;
637 };
638 swap_case_emul0_1f: emul0@1f,0 {
639 compatible = "sandbox,swap-case";
640 };
Simon Glass937bb472019-12-06 21:41:57 -0700641 p2sb_emul: emul@2,0 {
642 compatible = "sandbox,p2sb-emul";
643 };
Simon Glass8c501022019-12-06 21:41:54 -0700644 pmc_emul1e: emul@1e,0 {
645 compatible = "sandbox,pmc-emul";
646 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600647 };
648
Tom Rini4a3ca482020-02-11 12:41:23 -0500649 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700650 compatible = "sandbox,pci";
651 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500652 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700653 #address-cells = <3>;
654 #size-cells = <2>;
655 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
656 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700657 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200658 0x0c 0x00 0x1234 0x5678
659 0x10 0x00 0x1234 0x5678>;
660 pci@10,0 {
661 reg = <0x8000 0 0 0 0>;
662 };
Bin Meng408e5902018-08-03 01:14:41 -0700663 };
664
Tom Rini4a3ca482020-02-11 12:41:23 -0500665 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700666 compatible = "sandbox,pci";
667 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500668 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700669 #address-cells = <3>;
670 #size-cells = <2>;
671 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
672 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
673 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
674 pci@1f,0 {
675 compatible = "pci-generic";
676 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600677 sandbox,emul = <&swap_case_emul2_1f>;
678 };
679 };
680
681 pci-emul2 {
682 compatible = "sandbox,pci-emul-parent";
683 swap_case_emul2_1f: emul2@1f,0 {
684 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700685 };
686 };
687
Ramon Friedc64f19b2019-04-27 11:15:23 +0300688 pci_ep: pci_ep {
689 compatible = "sandbox,pci_ep";
690 };
691
Simon Glass9c433fe2017-04-23 20:10:44 -0600692 probing {
693 compatible = "simple-bus";
694 test1 {
695 compatible = "denx,u-boot-probe-test";
696 };
697
698 test2 {
699 compatible = "denx,u-boot-probe-test";
700 };
701
702 test3 {
703 compatible = "denx,u-boot-probe-test";
704 };
705
706 test4 {
707 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100708 first-syscon = <&syscon0>;
709 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100710 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600711 };
712 };
713
Stephen Warren92c67fa2016-07-13 13:45:31 -0600714 pwrdom: power-domain {
715 compatible = "sandbox,power-domain";
716 #power-domain-cells = <1>;
717 };
718
719 power-domain-test {
720 compatible = "sandbox,power-domain-test";
721 power-domains = <&pwrdom 2>;
722 };
723
Simon Glass5620cf82018-10-01 12:22:40 -0600724 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600725 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600726 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600727 };
728
729 pwm2 {
730 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600731 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600732 };
733
Simon Glass3d355e62015-07-06 12:54:31 -0600734 ram {
735 compatible = "sandbox,ram";
736 };
737
Simon Glassd860f222015-07-06 12:54:29 -0600738 reset@0 {
739 compatible = "sandbox,warm-reset";
740 };
741
742 reset@1 {
743 compatible = "sandbox,reset";
744 };
745
Stephen Warren6488e642016-06-17 09:43:59 -0600746 resetc: reset-ctl {
747 compatible = "sandbox,reset-ctl";
748 #reset-cells = <1>;
749 };
750
751 reset-ctl-test {
752 compatible = "sandbox,reset-ctl-test";
753 resets = <&resetc 100>, <&resetc 2>;
754 reset-names = "other", "test";
755 };
756
Sughosh Ganu23e37512019-12-28 23:58:31 +0530757 rng {
758 compatible = "sandbox,sandbox-rng";
759 };
760
Nishanth Menonedf85812015-09-17 15:42:41 -0500761 rproc_1: rproc@1 {
762 compatible = "sandbox,test-processor";
763 remoteproc-name = "remoteproc-test-dev1";
764 };
765
766 rproc_2: rproc@2 {
767 compatible = "sandbox,test-processor";
768 internal-memory-mapped;
769 remoteproc-name = "remoteproc-test-dev2";
770 };
771
Simon Glass5620cf82018-10-01 12:22:40 -0600772 panel {
773 compatible = "simple-panel";
774 backlight = <&backlight 0 100>;
775 };
776
Ramon Fried26ed32e2018-07-02 02:57:59 +0300777 smem@0 {
778 compatible = "sandbox,smem";
779 };
780
Simon Glass76072ac2018-12-10 10:37:36 -0700781 sound {
782 compatible = "sandbox,sound";
783 cpu {
784 sound-dai = <&i2s 0>;
785 };
786
787 codec {
788 sound-dai = <&audio 0>;
789 };
790 };
791
Simon Glass25348a42014-10-13 23:42:11 -0600792 spi@0 {
793 #address-cells = <1>;
794 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600795 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600796 compatible = "sandbox,spi";
797 cs-gpios = <0>, <&gpio_a 0>;
798 spi.bin@0 {
799 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000800 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600801 spi-max-frequency = <40000000>;
802 sandbox,filename = "spi.bin";
803 };
804 };
805
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100806 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600807 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200808 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600809 };
810
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100811 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600812 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600813 reg = <0x20 5
814 0x28 6
815 0x30 7
816 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600817 };
818
Patrick Delaunayee010432019-03-07 09:57:13 +0100819 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900820 compatible = "simple-mfd", "syscon";
821 reg = <0x40 5
822 0x48 6
823 0x50 7
824 0x58 8>;
825 };
826
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800827 timer {
828 compatible = "sandbox,timer";
829 clock-frequency = <1000000>;
830 };
831
Miquel Raynal80938c12018-05-15 11:57:27 +0200832 tpm2 {
833 compatible = "sandbox,tpm2";
834 };
835
Simon Glass5b968632015-05-22 15:42:15 -0600836 uart0: serial {
837 compatible = "sandbox,serial";
838 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500839 };
840
Simon Glass31680482015-03-25 12:23:05 -0600841 usb_0: usb@0 {
842 compatible = "sandbox,usb";
843 status = "disabled";
844 hub {
845 compatible = "sandbox,usb-hub";
846 #address-cells = <1>;
847 #size-cells = <0>;
848 flash-stick {
849 reg = <0>;
850 compatible = "sandbox,usb-flash";
851 };
852 };
853 };
854
855 usb_1: usb@1 {
856 compatible = "sandbox,usb";
857 hub {
858 compatible = "usb-hub";
859 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +0200860 #address-cells = <1>;
861 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -0600862 hub-emul {
863 compatible = "sandbox,usb-hub";
864 #address-cells = <1>;
865 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700866 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600867 reg = <0>;
868 compatible = "sandbox,usb-flash";
869 sandbox,filepath = "testflash.bin";
870 };
871
Simon Glass4700fe52015-11-08 23:48:01 -0700872 flash-stick@1 {
873 reg = <1>;
874 compatible = "sandbox,usb-flash";
875 sandbox,filepath = "testflash1.bin";
876 };
877
878 flash-stick@2 {
879 reg = <2>;
880 compatible = "sandbox,usb-flash";
881 sandbox,filepath = "testflash2.bin";
882 };
883
Simon Glassc0ccc722015-11-08 23:48:08 -0700884 keyb@3 {
885 reg = <3>;
886 compatible = "sandbox,usb-keyb";
887 };
888
Simon Glass31680482015-03-25 12:23:05 -0600889 };
Michael Walle7c961322020-06-02 01:47:07 +0200890
891 usbstor@1 {
892 reg = <1>;
893 };
894 usbstor@3 {
895 reg = <3>;
896 };
Simon Glass31680482015-03-25 12:23:05 -0600897 };
898 };
899
900 usb_2: usb@2 {
901 compatible = "sandbox,usb";
902 status = "disabled";
903 };
904
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200905 spmi: spmi@0 {
906 compatible = "sandbox,spmi";
907 #address-cells = <0x1>;
908 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600909 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200910 pm8916@0 {
911 compatible = "qcom,spmi-pmic";
912 reg = <0x0 0x1>;
913 #address-cells = <0x1>;
914 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600915 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200916
917 spmi_gpios: gpios@c000 {
918 compatible = "qcom,pm8916-gpio";
919 reg = <0xc000 0x400>;
920 gpio-controller;
921 gpio-count = <4>;
922 #gpio-cells = <2>;
923 gpio-bank-name="spmi";
924 };
925 };
926 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700927
928 wdt0: wdt@0 {
929 compatible = "sandbox,wdt";
930 };
Rob Clarka471b672018-01-10 11:33:30 +0100931
Mario Six95922152018-08-09 14:51:19 +0200932 axi: axi@0 {
933 compatible = "sandbox,axi";
934 #address-cells = <0x1>;
935 #size-cells = <0x1>;
936 store@0 {
937 compatible = "sandbox,sandbox_store";
938 reg = <0x0 0x400>;
939 };
940 };
941
Rob Clarka471b672018-01-10 11:33:30 +0100942 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700943 #address-cells = <1>;
944 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -0700945 setting = "sunrise ohoka";
946 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -0700947 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -0600948 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +0100949 chosen-test {
950 compatible = "denx,u-boot-fdt-test";
951 reg = <9 1>;
952 };
953 };
Mario Six35616ef2018-03-12 14:53:33 +0100954
955 translation-test@8000 {
956 compatible = "simple-bus";
957 reg = <0x8000 0x4000>;
958
959 #address-cells = <0x2>;
960 #size-cells = <0x1>;
961
962 ranges = <0 0x0 0x8000 0x1000
963 1 0x100 0x9000 0x1000
964 2 0x200 0xA000 0x1000
965 3 0x300 0xB000 0x1000
966 >;
967
Fabien Dessenne22236e02019-05-31 15:11:30 +0200968 dma-ranges = <0 0x000 0x10000000 0x1000
969 1 0x100 0x20000000 0x1000
970 >;
971
Mario Six35616ef2018-03-12 14:53:33 +0100972 dev@0,0 {
973 compatible = "denx,u-boot-fdt-dummy";
974 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100975 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100976 };
977
978 dev@1,100 {
979 compatible = "denx,u-boot-fdt-dummy";
980 reg = <1 0x100 0x1000>;
981
982 };
983
984 dev@2,200 {
985 compatible = "denx,u-boot-fdt-dummy";
986 reg = <2 0x200 0x1000>;
987 };
988
989
990 noxlatebus@3,300 {
991 compatible = "simple-bus";
992 reg = <3 0x300 0x1000>;
993
994 #address-cells = <0x1>;
995 #size-cells = <0x0>;
996
997 dev@42 {
998 compatible = "denx,u-boot-fdt-dummy";
999 reg = <0x42>;
1000 };
1001 };
1002 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001003
1004 osd {
1005 compatible = "sandbox,sandbox_osd";
1006 };
Tom Rinib93eea72018-09-30 18:16:51 -04001007
Mario Sixab664ff2018-07-31 11:44:13 +02001008 board {
1009 compatible = "sandbox,board_sandbox";
1010 };
Jens Wiklander86afaa62018-09-25 16:40:16 +02001011
1012 sandbox_tee {
1013 compatible = "sandbox,tee";
1014 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001015
1016 sandbox_virtio1 {
1017 compatible = "sandbox,virtio1";
1018 };
1019
1020 sandbox_virtio2 {
1021 compatible = "sandbox,virtio2";
1022 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001023
1024 pinctrl {
1025 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001026
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&gpios>;
1029
1030 gpios: gpios {
1031 gpio0 {
1032 pins = "GPIO0";
1033 bias-pull-up;
1034 input-disable;
1035 };
1036 gpio1 {
1037 pins = "GPIO1";
1038 output-high;
1039 drive-open-drain;
1040 };
1041 gpio2 {
1042 pins = "GPIO2";
1043 bias-pull-down;
1044 input-enable;
1045 };
1046 gpio3 {
1047 pins = "GPIO3";
1048 bias-disable;
1049 };
1050 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001051 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001052
1053 hwspinlock@0 {
1054 compatible = "sandbox,hwspinlock";
1055 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001056
1057 dma: dma {
1058 compatible = "sandbox,dma";
1059 #dma-cells = <1>;
1060
1061 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1062 dma-names = "m2m", "tx0", "rx0";
1063 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001064
Alex Marginean0649be52019-07-12 10:13:53 +03001065 /*
1066 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1067 * end of the test. If parent mdio is removed first, clean-up of the
1068 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1069 * active at the end of the test. That it turn doesn't allow the mdio
1070 * class to be destroyed, triggering an error.
1071 */
1072 mdio-mux-test {
1073 compatible = "sandbox,mdio-mux";
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1076 mdio-parent-bus = <&mdio>;
1077
1078 mdio-ch-test@0 {
1079 reg = <0>;
1080 };
1081 mdio-ch-test@1 {
1082 reg = <1>;
1083 };
1084 };
1085
1086 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001087 compatible = "sandbox,mdio";
1088 };
Sean Andersonb7860542020-06-24 06:41:12 -04001089
1090 pm-bus-test {
1091 compatible = "simple-pm-bus";
1092 clocks = <&clk_sandbox 4>;
1093 power-domains = <&pwrdom 1>;
1094 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001095
1096 resetc2: syscon-reset {
1097 compatible = "syscon-reset";
1098 #reset-cells = <1>;
1099 regmap = <&syscon0>;
1100 offset = <1>;
1101 mask = <0x27FFFFFF>;
1102 assert-high = <0>;
1103 };
1104
1105 syscon-reset-test {
1106 compatible = "sandbox,misc_sandbox";
1107 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1108 reset-names = "valid", "no_mask", "out_of_range";
1109 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001110};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001111
1112#include "sandbox_pmic.dtsi"