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Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +02001/*
2 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +02007 */
8
9#include <common.h>
Reinhard Meyerb06208c2010-11-07 13:26:14 +010010#include <asm/io.h>
Heiko Schocherf1e3a8c2014-10-31 08:31:04 +010011#include <asm/arch/at91sam9260_matrix.h>
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020012#include <asm/arch/at91_common.h>
13#include <asm/arch/at91_pmc.h>
Heiko Schocherf1e3a8c2014-10-31 08:31:04 +010014#include <asm/arch/at91sam9_sdramc.h>
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020015#include <asm/arch/gpio.h>
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020016
Reinhard Meyer6348f1d2010-08-25 12:32:53 +020017/*
18 * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
19 * peripheral pins. Good to have if hardware is soldered optionally
20 * or in case of SPI no slave is selected. Avoid lines to float
21 * needlessly. Use a short local PUP define.
22 *
23 * Due to errata "TXD floats when CTS is inactive" pullups are always
24 * on for TXD pins.
25 */
26#ifdef CONFIG_AT91_GPIO_PULLUP
27# define PUP CONFIG_AT91_GPIO_PULLUP
28#else
29# define PUP 0
30#endif
31
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020032void at91_serial0_hw_init(void)
33{
Reinhard Meyere260d0b2010-11-03 15:39:55 +010034 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010035
Jens Scharsigb49d15c2010-02-03 22:46:46 +010036 at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
Reinhard Meyer6348f1d2010-08-25 12:32:53 +020037 at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */
Reinhard Meyere260d0b2010-11-03 15:39:55 +010038 writel(1 << ATMEL_ID_USART0, &pmc->pcer);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020039}
40
41void at91_serial1_hw_init(void)
42{
Reinhard Meyere260d0b2010-11-03 15:39:55 +010043 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010044
Jens Scharsigb49d15c2010-02-03 22:46:46 +010045 at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
Reinhard Meyer6348f1d2010-08-25 12:32:53 +020046 at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */
Reinhard Meyere260d0b2010-11-03 15:39:55 +010047 writel(1 << ATMEL_ID_USART1, &pmc->pcer);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020048}
49
50void at91_serial2_hw_init(void)
51{
Reinhard Meyere260d0b2010-11-03 15:39:55 +010052 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010053
Jens Scharsigb49d15c2010-02-03 22:46:46 +010054 at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
Reinhard Meyer6348f1d2010-08-25 12:32:53 +020055 at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */
Reinhard Meyere260d0b2010-11-03 15:39:55 +010056 writel(1 << ATMEL_ID_USART2, &pmc->pcer);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020057}
58
Reinhard Meyere260d0b2010-11-03 15:39:55 +010059void at91_seriald_hw_init(void)
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020060{
Reinhard Meyere260d0b2010-11-03 15:39:55 +010061 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010062
Reinhard Meyer6348f1d2010-08-25 12:32:53 +020063 at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */
Jens Scharsigb49d15c2010-02-03 22:46:46 +010064 at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
Reinhard Meyere260d0b2010-11-03 15:39:55 +010065 writel(1 << ATMEL_ID_SYS, &pmc->pcer);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020066}
67
Albin Tonnerre4f572d82009-08-24 18:03:26 +020068#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020069void at91_spi0_hw_init(unsigned long cs_mask)
70{
Reinhard Meyere260d0b2010-11-03 15:39:55 +010071 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010072
Reinhard Meyer6348f1d2010-08-25 12:32:53 +020073 at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
74 at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
75 at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020076
77 /* Enable clock */
Reinhard Meyere260d0b2010-11-03 15:39:55 +010078 writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020079
80 if (cs_mask & (1 << 0)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +010081 at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020082 }
83 if (cs_mask & (1 << 1)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +010084 at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020085 }
86 if (cs_mask & (1 << 2)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +010087 at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020088 }
89 if (cs_mask & (1 << 3)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +010090 at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020091 }
92 if (cs_mask & (1 << 4)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +010093 at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020094 }
95 if (cs_mask & (1 << 5)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +010096 at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +020097 }
98 if (cs_mask & (1 << 6)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +010099 at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200100 }
101 if (cs_mask & (1 << 7)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100102 at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200103 }
104}
105
106void at91_spi1_hw_init(unsigned long cs_mask)
107{
Reinhard Meyere260d0b2010-11-03 15:39:55 +0100108 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
Jens Scharsiga4db1ca2010-02-03 22:46:58 +0100109
Reinhard Meyer6348f1d2010-08-25 12:32:53 +0200110 at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
111 at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
112 at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200113
114 /* Enable clock */
Reinhard Meyere260d0b2010-11-03 15:39:55 +0100115 writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200116
117 if (cs_mask & (1 << 0)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100118 at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200119 }
120 if (cs_mask & (1 << 1)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100121 at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200122 }
123 if (cs_mask & (1 << 2)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100124 at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200125 }
126 if (cs_mask & (1 << 3)) {
Reinhard Meyer3da7e352011-07-25 21:56:04 +0000127 at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200128 }
129 if (cs_mask & (1 << 4)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100130 at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200131 }
132 if (cs_mask & (1 << 5)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100133 at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200134 }
135 if (cs_mask & (1 << 6)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100136 at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200137 }
138 if (cs_mask & (1 << 7)) {
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100139 at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200140 }
141}
142#endif
143
144#ifdef CONFIG_MACB
145void at91_macb_hw_init(void)
146{
Markus Hubig33d678e2012-08-07 17:43:22 +0200147 /* Enable EMAC clock */
148 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
149 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
150
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100151 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
152 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
153 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */
154 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */
155 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */
156 at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */
157 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */
158 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */
159 at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */
160 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200161
162#ifndef CONFIG_RMII
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100163 at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */
164 at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */
165 at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */
166 at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */
167 at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */
Jean-Christophe PLAGNIOL-VILLARD56dc2fd2009-05-16 10:02:05 +0200168#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200169 /*
170 * use PA10, PA11 for ETX2, ETX3.
171 * PA23 and PA24 are for TWI EEPROM
172 */
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100173 at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */
174 at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200175#else
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100176 at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */
177 at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */
Reinhard Meyer146775f2010-12-01 05:49:53 +0100178#if defined(CONFIG_AT91SAM9G20)
179 /* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
180 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
181 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
182#endif
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200183#endif
Jens Scharsigb49d15c2010-02-03 22:46:46 +0100184 at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */
Jean-Christophe PLAGNIOL-VILLARD2495b2d2009-05-13 21:01:13 +0200185#endif
186}
187#endif
Reinhard Meyerc718a562010-08-13 10:31:06 +0200188
Sven Schnelle69df6de2011-10-21 14:49:26 +0200189#if defined(CONFIG_GENERIC_ATMEL_MCI)
Reinhard Meyerc718a562010-08-13 10:31:06 +0200190void at91_mci_hw_init(void)
191{
Wu, Josh1a500d62013-03-28 20:28:41 +0000192 /* Enable mci clock */
193 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
194 writel(1 << ATMEL_ID_MCI, &pmc->pcer);
195
Reinhard Meyerc718a562010-08-13 10:31:06 +0200196 at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */
197#if defined(CONFIG_ATMEL_MCI_PORTB)
198 at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */
199 at91_set_b_periph(AT91_PIO_PORTA, 0, 1); /* MCDB0 */
200 at91_set_b_periph(AT91_PIO_PORTA, 5, 1); /* MCDB1 */
201 at91_set_b_periph(AT91_PIO_PORTA, 4, 1); /* MCDB2 */
202 at91_set_b_periph(AT91_PIO_PORTA, 3, 1); /* MCDB3 */
203#else
204 at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* MCCDA */
205 at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* MCDA0 */
206 at91_set_a_periph(AT91_PIO_PORTA, 9, 1); /* MCDA1 */
207 at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* MCDA2 */
208 at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* MCDA3 */
209#endif
210}
211#endif
Heiko Schocherf1e3a8c2014-10-31 08:31:04 +0100212
213void at91_sdram_hw_init(void)
214{
215 at91_set_a_periph(AT91_PIO_PORTC, 16, 0);
216 at91_set_a_periph(AT91_PIO_PORTC, 17, 0);
217 at91_set_a_periph(AT91_PIO_PORTC, 18, 0);
218 at91_set_a_periph(AT91_PIO_PORTC, 19, 0);
219 at91_set_a_periph(AT91_PIO_PORTC, 20, 0);
220 at91_set_a_periph(AT91_PIO_PORTC, 21, 0);
221 at91_set_a_periph(AT91_PIO_PORTC, 22, 0);
222 at91_set_a_periph(AT91_PIO_PORTC, 23, 0);
223 at91_set_a_periph(AT91_PIO_PORTC, 24, 0);
224 at91_set_a_periph(AT91_PIO_PORTC, 25, 0);
225 at91_set_a_periph(AT91_PIO_PORTC, 26, 0);
226 at91_set_a_periph(AT91_PIO_PORTC, 27, 0);
227 at91_set_a_periph(AT91_PIO_PORTC, 28, 0);
228 at91_set_a_periph(AT91_PIO_PORTC, 29, 0);
229 at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
230 at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
231}