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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +02002/*
3 * WORK Microwave work_92105 board configuration file
4 *
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +02007 */
8
9#ifndef __CONFIG_WORK_92105_H__
10#define __CONFIG_WORK_92105_H__
11
12/* SoC and board defines */
13#include <linux/sizes.h>
14#include <asm/arch/cpu.h>
15
16/*
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020017 * Memory configurations
18 */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020019#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
20#define CONFIG_SYS_SDRAM_SIZE SZ_128M
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020021
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020022#define CONFIG_RTC_DS1374
23
24/*
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020025 * U-Boot General Configurations
26 */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020027
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020028/*
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020029 * NAND chip timings for FIXME: which one?
30 */
31
32#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
33#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
34#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
35#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
36#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
37#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
38#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
39
40/*
41 * NAND
42 */
43
44/* driver configuration */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020045#define CONFIG_SYS_MAX_NAND_DEVICE 1
46#define CONFIG_SYS_MAX_NAND_CHIPS 1
47#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020048
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020049/*
50 * GPIO
51 */
52
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020053/*
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020054 * Environment
55 */
56
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020057/*
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020058 * SPL
59 */
60
61/* SPL will be executed at offset 0 */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020062/* SPL will use SRAM as stack */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020063/* Use the framework and generic lib */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020064/* SPL will use serial */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020065/* SPL will load U-Boot from NAND offset 0x40000 */
Albert ARIBAUD \(3ADEV\)ee69a392015-03-31 11:40:51 +020066/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
67#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
68#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
69#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
70
71/*
72 * Include SoC specific configuration
73 */
74#include <asm/arch/config.h>
75
76#endif /* __CONFIG_WORK_92105_H__*/