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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocherc8f51122010-03-05 07:36:33 +01002/*
3 * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
4 *
5 * based on:
6 * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
Heiko Schocherc8f51122010-03-05 07:36:33 +01007 */
8
9#ifndef __IMX27LITE_COMMON_CONFIG_H
10#define __IMX27LITE_COMMON_CONFIG_H
11
12/*
13 * SoC Configuration
14 */
Heiko Schocherc8f51122010-03-05 07:36:33 +010015#define CONFIG_MX27
16#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
Heiko Schocherc8f51122010-03-05 07:36:33 +010017
Heiko Schocherc8f51122010-03-05 07:36:33 +010018/*
19 * Lowlevel configuration
20 */
21#define SDRAM_ESDCFG_REGISTER_VAL(cas) \
22 (ESDCFG_TRC(10) | \
23 ESDCFG_TRCD(3) | \
24 ESDCFG_TCAS(cas) | \
25 ESDCFG_TRRD(1) | \
26 ESDCFG_TRAS(5) | \
27 ESDCFG_TWR | \
28 ESDCFG_TMRD(2) | \
29 ESDCFG_TRP(2) | \
30 ESDCFG_TXP(3))
31
32#define SDRAM_ESDCTL_REGISTER_VAL \
33 (ESDCTL_PRCT(0) | \
34 ESDCTL_BL | \
35 ESDCTL_PWDT(0) | \
36 ESDCTL_SREFR(3) | \
37 ESDCTL_DSIZ_32 | \
38 ESDCTL_COL10 | \
39 ESDCTL_ROW13 | \
40 ESDCTL_SDE)
41
42#define SDRAM_ALL_VAL 0xf00
43
44#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */
45#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
46
47#define MPCTL0_VAL 0x1ef15d5
48
49#define SPCTL0_VAL 0x043a1c09
50
51#define CSCR_VAL 0x33f08107
52
53#define PCDR0_VAL 0x120470c3
54#define PCDR1_VAL 0x03030303
55#define PCCR0_VAL 0xffffffff
56#define PCCR1_VAL 0xfffffffc
57
58#define AIPI1_PSR0_VAL 0x20040304
59#define AIPI1_PSR1_VAL 0xdffbfcfb
60#define AIPI2_PSR0_VAL 0x07ffc200
61#define AIPI2_PSR1_VAL 0xffffffff
62
63/*
64 * Memory Info
65 */
Heiko Schocherc8f51122010-03-05 07:36:33 +010066/* memtest start address */
Heiko Schocherc8f51122010-03-05 07:36:33 +010067#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
68#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
69
70/*
71 * Serial Driver info
72 */
Marek Vasut46967a72022-04-24 23:44:04 +020073#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
Heiko Schocherc8f51122010-03-05 07:36:33 +010074
75/*
76 * Flash & Environment
77 */
Heiko Schocherc8f51122010-03-05 07:36:33 +010078/* Use buffered writes (~10x faster) */
Heiko Schocherc8f51122010-03-05 07:36:33 +010079/* Use hardware sector protection */
Heiko Schocherc8f51122010-03-05 07:36:33 +010080/* CS2 Base address */
81#define PHYS_FLASH_1 0xc0000000
82/* Flash Base for U-Boot */
83#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
84#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \
85 CONFIG_SYS_FLASH_SECT_SZ)
Heiko Schocherc8f51122010-03-05 07:36:33 +010086#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
Heiko Schocherc8f51122010-03-05 07:36:33 +010087/* Address and size of Redundant Environment Sector */
Heiko Schocherc8f51122010-03-05 07:36:33 +010088
89/*
90 * Ethernet
91 */
Heiko Schocherc8f51122010-03-05 07:36:33 +010092#define CONFIG_FEC_MXC_PHYADDR 0x1f
Heiko Schocherc8f51122010-03-05 07:36:33 +010093
94/*
95 * MTD
96 */
Heiko Schocherc8f51122010-03-05 07:36:33 +010097
98/*
99 * NAND
100 */
Heiko Schocherc8f51122010-03-05 07:36:33 +0100101#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
102#define CONFIG_SYS_MAX_NAND_DEVICE 1
103#define CONFIG_SYS_NAND_BASE 0xd8000000
Heiko Schocherc8f51122010-03-05 07:36:33 +0100104#define CONFIG_MXC_NAND_HWECC
Heiko Schocherc8f51122010-03-05 07:36:33 +0100105
106/*
Heiko Schocherc8f51122010-03-05 07:36:33 +0100107 * U-Boot general configuration
108 */
Heiko Schocherc8f51122010-03-05 07:36:33 +0100109#define CONFIG_EXTRA_ENV_SETTINGS \
110 "netdev=eth0\0" \
111 "nfsargs=setenv bootargs root=/dev/nfs rw " \
112 "nfsroot=${serverip}:${rootpath}\0" \
113 "ramargs=setenv bootargs root=/dev/ram rw\0" \
114 "addip=setenv bootargs ${bootargs} " \
115 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
116 ":${hostname}:${netdev}:off panic=1\0" \
117 "addtty=setenv bootargs ${bootargs}" \
118 " console=ttymxc0,${baudrate}\0" \
119 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
120 "addmisc=setenv bootargs ${bootargs}\0" \
Mario Six790d8442018-03-28 14:38:20 +0200121 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
Heiko Schocherc8f51122010-03-05 07:36:33 +0100122 "kernel_addr_r=a0800000\0" \
Mario Six790d8442018-03-28 14:38:20 +0200123 "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
Heiko Schocherc8f51122010-03-05 07:36:33 +0100124 "rootpath=/opt/eldk-4.2-arm/arm\0" \
125 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
126 "run nfsargs addip addtty addmtd addmisc;" \
127 "bootm\0" \
Marek Vasutfd5ba892012-09-23 17:41:23 +0200128 "bootcmd=run net_nfs\0" \
Heiko Schocherc8f51122010-03-05 07:36:33 +0100129 "load=tftp ${loadaddr} ${u-boot}\0" \
Marek Vasutfd5ba892012-09-23 17:41:23 +0200130 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
131 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
Heiko Schocherc8f51122010-03-05 07:36:33 +0100132 " +${filesize};cp.b ${fileaddr} " \
Marek Vasutfd5ba892012-09-23 17:41:23 +0200133 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
Heiko Schocherc8f51122010-03-05 07:36:33 +0100134 "upd=run load update\0" \
Heiko Schocherc8f51122010-03-05 07:36:33 +0100135
Heiko Schocherd6d60622010-09-22 14:06:33 +0200136/* additions for new relocation code, must be added to all boards */
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200137#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Heiko Schocherc8f51122010-03-05 07:36:33 +0100138#endif /* __IMX27LITE_COMMON_CONFIG_H */