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git01.mediatek.com / filogic / uboot / 4d42431e0c83c791fad9f9defbc0a1531e864e59 / . / board / Marvell / mv88f6281gtw_ge / mv88f6281gtw_ge.c
blob: fb57faa52bf3fe2e62c9d4d3fec85e331d422993 [file] [log] [blame]
Prafulla Wadaskar60a04f92009-07-16 20:58:01 +0530[diff] [blame]1/*
2 * Maintainer : Prafulla Wadaskar <prafulla@marvell.com>
3 *
4 * (C) Copyright 2009
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 */
26
27#include <common.h>
28#include <netdev.h>
Lei Wen298ae912011-10-18 20:11:42 +0530[diff] [blame]29#include <asm/arch/cpu.h>
Prafulla Wadaskar60a04f92009-07-16 20:58:01 +0530[diff] [blame]30#include <asm/arch/kirkwood.h>
31#include <asm/arch/mpp.h>
32#include "mv88f6281gtw_ge.h"
33
34DECLARE_GLOBAL_DATA_PTR;
35
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]36int board_early_init_f(void)
Prafulla Wadaskar60a04f92009-07-16 20:58:01 +0530[diff] [blame]37{
38 /*
39 * default gpio configuration
40 * There are maximum 64 gpios controlled through 2 sets of registers
41 * the below configuration configures mainly initial LED status
42 */
43 kw_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
44 MV88F6281GTW_GE_OE_VAL_HIGH,
45 MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
46
47 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame^]48 static const u32 kwmpp_config[] = {
Prafulla Wadaskar60a04f92009-07-16 20:58:01 +0530[diff] [blame]49 MPP0_SPI_SCn,
50 MPP1_SPI_MOSI,
51 MPP2_SPI_SCK,
52 MPP3_SPI_MISO,
53 MPP4_GPIO,
54 MPP5_GPO,
55 MPP6_SYSRST_OUTn,
56 MPP7_SPI_SCn,
57 MPP8_TW_SDA,
58 MPP9_TW_SCK,
59 MPP10_UART0_TXD,
60 MPP11_UART0_RXD,
61 MPP12_GPO,
62 MPP13_GPIO,
63 MPP14_GPIO,
64 MPP15_GPIO,
65 MPP16_GPIO,
66 MPP17_GPIO,
67 MPP18_GPO,
68 MPP19_GPO,
69 MPP20_GPIO,
70 MPP21_GPIO,
71 MPP22_GPIO,
72 MPP23_GPIO,
73 MPP24_GPIO,
74 MPP25_GPIO,
75 MPP26_GPIO,
76 MPP27_GPIO,
77 MPP28_GPIO,
78 MPP29_GPIO,
79 MPP30_GPIO,
80 MPP31_GPIO,
81 MPP32_GPIO,
82 MPP33_GPIO,
83 MPP34_GPIO,
84 MPP35_GPIO,
85 MPP36_GPIO,
86 MPP37_GPIO,
87 MPP38_GPIO,
88 MPP39_GPIO,
89 MPP40_GPIO,
90 MPP41_GPIO,
91 MPP42_GPIO,
92 MPP43_GPIO,
93 MPP44_GPIO,
94 MPP45_GPIO,
95 MPP46_GPIO,
96 MPP47_GPIO,
97 MPP48_GPIO,
98 MPP49_GPIO,
99 0
100 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]101 kirkwood_mpp_conf(kwmpp_config, NULL);
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]102 return 0;
103}
Prafulla Wadaskar60a04f92009-07-16 20:58:01 +0530[diff] [blame]104
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]105int board_init(void)
106{
Prafulla Wadaskar60a04f92009-07-16 20:58:01 +0530[diff] [blame]107 /*
108 * arch number of board
109 */
110 gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE;
111
112 /* adress of boot parameters */
113 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
114
115 return 0;
116}
117
Prafulla Wadaskar60a04f92009-07-16 20:58:01 +0530[diff] [blame]118#ifdef CONFIG_MV88E61XX_SWITCH
119void reset_phy(void)
120{
121 /* configure and initialize switch */
122 struct mv88e61xx_config swcfg = {
123 .name = "egiga0",
124 .vlancfg = MV88E61XX_VLANCFG_ROUTER,
125 .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
126 .led_init = MV88E61XX_LED_INIT_EN,
127 .mdip = MV88E61XX_MDIP_REVERSE,
128 .portstate = MV88E61XX_PORTSTT_FORWARDING,
129 .cpuport = (1 << 5),
130 .ports_enabled = 0x3f
131 };
132
133 mv88e61xx_switch_initialize(&swcfg);
134}
135#endif /* CONFIG_MV88E61XX_SWITCH */