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git01.mediatek.com / filogic / uboot / 4d2cc55c3bb1372c2f51ded486250a79e35db0ca / . / arch / arm / dts / r8a77965-u-boot.dtsi
blob: cbd29b3aed682bcbfd1b8905e8ce0eb82c998f32 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasuta8c01e02018-02-26 10:35:15 +0100[diff] [blame]2/*
3 * Device Tree Source extras for U-Boot on RCar R8A77965 SoC
4 *
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
Marek Vasuta8c01e02018-02-26 10:35:15 +0100[diff] [blame]6 */
7
8#include "r8a779x-u-boot.dtsi"
9
10&extalr_clk {
11 u-boot,dm-pre-reloc;
12};
Marek Vasut3e7ae7e32018-12-03 20:17:50 +0100[diff] [blame]13
14&soc {
15 rpc: rpc@0xee200000 {
16 compatible = "renesas,rpc-r8a77965", "renesas,rpc";
17 reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
18 clocks = <&cpg CPG_MOD 917>;
19 bank-width = <2>;
20 status = "disabled";
21 };
Marek Vasutb2e2fe32018-12-03 20:34:13 +0100[diff] [blame]22
Marek Vasut3b7dffe2018-12-03 20:39:07 +0100[diff] [blame]23 sdhi0: sd@ee100000 {
24 compatible = "renesas,sdhi-r8a77965";
25 reg = <0 0xee100000 0 0x2000>;
26 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
27 clocks = <&cpg CPG_MOD 314>;
28 max-frequency = <200000000>;
29 power-domains = <&sysc 32>;
30 resets = <&cpg 314>;
31 status = "disabled";
32 };
33
34 sdhi1: sd@ee120000 {
35 compatible = "renesas,sdhi-r8a77965";
36 reg = <0 0xee120000 0 0x2000>;
37 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&cpg CPG_MOD 313>;
39 max-frequency = <200000000>;
40 power-domains = <&sysc 32>;
41 resets = <&cpg 313>;
42 status = "disabled";
43 };
44
45 sdhi2: sd@ee140000 {
46 compatible = "renesas,sdhi-r8a77965";
47 reg = <0 0xee140000 0 0x2000>;
48 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
49 clocks = <&cpg CPG_MOD 312>;
50 max-frequency = <200000000>;
51 power-domains = <&sysc 32>;
52 resets = <&cpg 312>;
53 status = "disabled";
54 };
55
56 sdhi3: sd@ee160000 {
57 compatible = "renesas,sdhi-r8a77965";
58 reg = <0 0xee160000 0 0x2000>;
59 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
60 clocks = <&cpg CPG_MOD 311>;
61 max-frequency = <200000000>;
62 power-domains = <&sysc 32>;
63 resets = <&cpg 311>;
64 status = "disabled";
65 };
66
Marek Vasutb2e2fe32018-12-03 20:34:13 +0100[diff] [blame]67 ehci0: usb@ee080100 {
68 compatible = "generic-ehci";
69 reg = <0 0xee080100 0 0x100>;
70 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&cpg CPG_MOD 703>;
72 phys = <&usb2_phy0>;
73 phy-names = "usb";
74 companion= <&ohci0>;
75 power-domains = <&sysc 32>;
76 resets = <&cpg 703>;
77 };
78
79 usb2_phy0: usb-phy@ee080200 {
80 compatible = "renesas,usb2-phy-r8a77965",
81 "renesas,rcar-gen3-usb2-phy";
82 reg = <0 0xee080200 0 0x700>;
83 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&cpg CPG_MOD 703>;
85 power-domains = <&sysc 32>;
86 resets = <&cpg 703>;
87 #phy-cells = <0>;
88 };
89
90 ehci1: usb@ee0a0100 {
91 compatible = "generic-ehci";
92 reg = <0 0xee0a0100 0 0x100>;
93 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&cpg CPG_MOD 702>;
95 phys = <&usb2_phy1>;
96 phy-names = "usb";
97 companion= <&ohci1>;
98 power-domains = <&sysc 32>;
99 resets = <&cpg 702>;
100 };
101
102 usb2_phy1: usb-phy@ee0a0200 {
103 compatible = "renesas,usb2-phy-r8a77965",
104 "renesas,rcar-gen3-usb2-phy";
105 reg = <0 0xee0a0200 0 0x700>;
106 clocks = <&cpg CPG_MOD 702>;
107 power-domains = <&sysc 32>;
108 resets = <&cpg 702>;
109 #phy-cells = <0>;
110 };
111
112 xhci0: usb@ee000000 {
113 compatible = "renesas,xhci-r8a77965",
114 "renesas,rcar-gen3-xhci";
115 reg = <0 0xee000000 0 0xc00>;
116 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&cpg CPG_MOD 328>;
118 power-domains = <&sysc 32>;
119 resets = <&cpg 328>;
120 };
Marek Vasut3e7ae7e32018-12-03 20:17:50 +0100[diff] [blame]121};