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git01.mediatek.com / filogic / uboot / 4cb7fbf4ff13b9488b733e8c3836e6b20c83e70b / . / arch / powerpc / include / asm / fsl_liodn.h
blob: 4c17fe232e63496413833cce1117f60bc81912a7 [file] [log] [blame]
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]1/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef _FSL_LIODN_H_
24#define _FSL_LIODN_H_
25
26#include <asm/types.h>
27
28struct liodn_id_table {
29 const char * compat;
30 u32 id[2];
31 u8 num_ids;
32 phys_addr_t compat_offset;
33 unsigned long reg_offset;
34};
35
36extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid);
37extern void set_liodns(void);
38extern void fdt_fixup_liodn(void *blob);
39
40#define SET_LIODN_BASE_1(idA) \
41 { .id = { idA }, .num_ids = 1, }
42
43#define SET_LIODN_BASE_2(idA, idB) \
44 { .id = { idA, idB }, .num_ids = 2 }
45
46#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
47 { .compat = name, \
48 .id = { idA }, .num_ids = 1, \
49 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
50 .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
51 }
52
53#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
54 { .compat = name, \
55 .id = { idA, idB }, .num_ids = 2, \
56 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
57 .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
58 }
59
60#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
61 SET_LIODN_ENTRY_1(compat, liodn, \
62 offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
63 compatoff)
64
65#define SET_USB_LIODN(usbNum, compat, liodn) \
66 SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
67 CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
68
69#define SET_SATA_LIODN(sataNum, liodn) \
70 SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
71 CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
72
73#define SET_PCI_LIODN(pciNum, liodn) \
74 SET_GUTS_LIODN("fsl,p4080-pcie", liodn, pex##pciNum##liodnr,\
75 CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
76
77/* reg nodes for DMA start @ 0x300 */
78#define SET_DMA_LIODN(dmaNum, liodn) \
79 SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
80 CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
81
82#define SET_SDHC_LIODN(sdhcNum, liodn) \
83 SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
84 CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
85
86#define SET_QMAN_LIODN(liodn) \
87 SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
88 CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \
89 CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
90
91#define SET_BMAN_LIODN(liodn) \
92 SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
93 CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \
94 CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
95
96#define SET_PME_LIODN(liodn) \
97 SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
98 CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
99 CONFIG_SYS_FSL_CORENET_PME_OFFSET)
100
101/* -1 from portID due to how immap has the registers */
102#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
103 CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
104 offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
105
106/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
107#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
108 SET_LIODN_ENTRY_1("fsl,fman-port-1g-rx", liodn, \
109 FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
110 CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \
111
112/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
113#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
114 SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \
115 FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
116 CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \
117
Kumar Gala1c9cee92010-08-17 23:12:37 -0500[diff] [blame]118#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
119 SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
120 offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]121 CONFIG_SYS_FSL_SEC_OFFSET, \
Kumar Gala1c9cee92010-08-17 23:12:37 -0500[diff] [blame]122 CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
Kumar Gala38449a42009-09-10 03:02:13 -0500[diff] [blame]123
124/* This is a bit evil since we treat rtic param as both a string & hex value */
125#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
126 SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
127 liodnA, \
128 offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
129 CONFIG_SYS_FSL_SEC_OFFSET, \
130 CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
131
132#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
133 SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
134 offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
135 CONFIG_SYS_FSL_SEC_OFFSET, 0)
136
137extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
138extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
139extern int liodn_tbl_sz, sec_liodn_tbl_sz;
140extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
141
142#endif