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git01.mediatek.com / filogic / uboot / 4ca48c9bcf0de35ea467d3a8f0a778c9e86345f5 / . / board / freescale / common / dcu_sii9022a.c
blob: 3bf71abf553fe8918c79eaf73a7fdc3f5fd5bf37 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Wang Huan183aa102014-09-05 13:52:49 +0800[diff] [blame]2/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Wang Huan183aa102014-09-05 13:52:49 +0800[diff] [blame]4 */
5
6#include <asm/io.h>
7#include <common.h>
8#include <fsl_dcu_fb.h>
9#include <i2c.h>
10#include <linux/fb.h>
11
12#define PIXEL_CLK_LSB_REG 0x00
13#define PIXEL_CLK_MSB_REG 0x01
14#define VERT_FREQ_LSB_REG 0x02
15#define VERT_FREQ_MSB_REG 0x03
16#define TOTAL_PIXELS_LSB_REG 0x04
17#define TOTAL_PIXELS_MSB_REG 0x05
18#define TOTAL_LINES_LSB_REG 0x06
19#define TOTAL_LINES_MSB_REG 0x07
20#define TPI_INBUS_FMT_REG 0x08
21#define TPI_INPUT_FMT_REG 0x09
22#define TPI_OUTPUT_FMT_REG 0x0A
23#define TPI_SYS_CTRL_REG 0x1A
24#define TPI_PWR_STAT_REG 0x1E
25#define TPI_AUDIO_HANDING_REG 0x25
26#define TPI_AUDIO_INTF_REG 0x26
27#define TPI_AUDIO_FREQ_REG 0x27
28#define TPI_SET_PAGE_REG 0xBC
29#define TPI_SET_OFFSET_REG 0xBD
30#define TPI_RW_ACCESS_REG 0xBE
31#define TPI_TRANS_MODE_REG 0xC7
32
33#define TPI_INBUS_CLOCK_RATIO_1 (1 << 6)
34#define TPI_INBUS_FULL_PIXEL_WIDE (1 << 5)
35#define TPI_INBUS_RISING_EDGE (1 << 4)
36#define TPI_INPUT_CLR_DEPTH_8BIT (0 << 6)
37#define TPI_INPUT_VRANGE_EXPAN_AUTO (0 << 2)
38#define TPI_INPUT_CLR_RGB (0 << 0)
39#define TPI_OUTPUT_CLR_DEPTH_8BIT (0 << 6)
40#define TPI_OUTPUT_VRANGE_COMPRE_AUTO (0 << 2)
41#define TPI_OUTPUT_CLR_HDMI_RGB (0 << 0)
42#define TPI_SYS_TMDS_OUTPUT (0 << 4)
43#define TPI_SYS_AV_NORAML (0 << 3)
44#define TPI_SYS_AV_MUTE (1 << 3)
45#define TPI_SYS_DVI_MODE (0 << 0)
46#define TPI_SYS_HDMI_MODE (1 << 0)
47#define TPI_PWR_STAT_MASK (3 << 0)
48#define TPI_PWR_STAT_D0 (0 << 0)
49#define TPI_AUDIO_PASS_BASIC (0 << 0)
50#define TPI_AUDIO_INTF_I2S (2 << 6)
51#define TPI_AUDIO_INTF_NORMAL (0 << 4)
52#define TPI_AUDIO_TYPE_PCM (1 << 0)
53#define TPI_AUDIO_SAMP_SIZE_16BIT (1 << 6)
54#define TPI_AUDIO_SAMP_FREQ_44K (2 << 3)
55#define TPI_SET_PAGE_SII9022A 0x01
56#define TPI_SET_OFFSET_SII9022A 0x82
57#define TPI_RW_EN_SRC_TERMIN (1 << 0)
58#define TPI_TRANS_MODE_ENABLE (0 << 7)
59
60/* Programming of Silicon SIi9022a HDMI Transmitter */
61int dcu_set_dvi_encoder(struct fb_videomode *videomode)
62{
63 u8 temp;
64 u16 temp1, temp2;
65 u32 temp3;
66
67 i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
68
69 /* Enable TPI transmitter mode */
70 temp = TPI_TRANS_MODE_ENABLE;
71 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, &temp, 1);
72
73 /* Enter into D0 state, full operation */
74 i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
75 temp &= ~TPI_PWR_STAT_MASK;
76 temp |= TPI_PWR_STAT_D0;
77 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
78
79 /* Enable source termination */
80 temp = TPI_SET_PAGE_SII9022A;
81 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, &temp, 1);
82 temp = TPI_SET_OFFSET_SII9022A;
83 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, &temp, 1);
84
85 i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
86 temp |= TPI_RW_EN_SRC_TERMIN;
87 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
88
89 /* Set TPI system control */
90 temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
91 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, &temp, 1);
92
93 /* Set pixel clock */
94 temp1 = PICOS2KHZ(videomode->pixclock) / 10;
95 temp = (u8)(temp1 & 0xFF);
96 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_LSB_REG, 1, &temp, 1);
97 temp = (u8)(temp1 >> 8);
98 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_MSB_REG, 1, &temp, 1);
99
100 /* Set total pixels per line */
101 temp1 = videomode->hsync_len + videomode->left_margin +
102 videomode->xres + videomode->right_margin;
103 temp = (u8)(temp1 & 0xFF);
104 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_LSB_REG, 1, &temp, 1);
105 temp = (u8)(temp1 >> 8);
106 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_MSB_REG, 1, &temp, 1);
107
108 /* Set total lines */
109 temp2 = videomode->vsync_len + videomode->upper_margin +
110 videomode->yres + videomode->lower_margin;
111 temp = (u8)(temp2 & 0xFF);
112 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_LSB_REG, 1, &temp, 1);
113 temp = (u8)(temp2 >> 8);
114 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_MSB_REG, 1, &temp, 1);
115
116 /* Set vertical frequency in Hz */
117 temp3 = temp1 * temp2;
118 temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
119 temp1 = (u16)temp3 * 100;
120 temp = (u8)(temp1 & 0xFF);
121 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_LSB_REG, 1, &temp, 1);
122 temp = (u8)(temp1 >> 8);
123 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_MSB_REG, 1, &temp, 1);
124
125 /* Set TPI input bus and pixel repetition data */
126 temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
127 TPI_INBUS_RISING_EDGE;
128 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INBUS_FMT_REG, 1, &temp, 1);
129
130 /* Set TPI AVI Input format data */
131 temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
132 TPI_INPUT_CLR_RGB;
133 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INPUT_FMT_REG, 1, &temp, 1);
134
135 /* Set TPI AVI Output format data */
136 temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
137 TPI_OUTPUT_CLR_HDMI_RGB;
138 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_OUTPUT_FMT_REG, 1, &temp, 1);
139
140 /* Set TPI audio configuration write data */
141 temp = TPI_AUDIO_PASS_BASIC;
142 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_HANDING_REG, 1, &temp, 1);
143
144 temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
145 TPI_AUDIO_TYPE_PCM;
146 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_INTF_REG, 1, &temp, 1);
147
148 temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
149 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1);
150
151 return 0;
152}