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git01.mediatek.com / filogic / uboot / 4ca48c9bcf0de35ea467d3a8f0a778c9e86345f5 / . / board / cloudengines / pogo_e02 / pogo_e02.c
blob: ffbd099c4ee49dac055f80aad867920540ad65f0 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]2/*
3 * Copyright (C) 2012
4 * David Purdy <david.c.purdy@gmail.com>
5 *
6 * Based on Kirkwood support:
7 * (C) Copyright 2009
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]10 */
11
12#include <common.h>
13#include <miiphy.h>
14#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]15#include <asm/arch/soc.h>
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]16#include <asm/arch/mpp.h>
17#include "pogo_e02.h"
18
19DECLARE_GLOBAL_DATA_PTR;
20
21int board_early_init_f(void)
22{
23 /*
24 * default gpio configuration
25 * There are maximum 64 gpios controlled through 2 sets of registers
26 * the below configuration configures mainly initial LED status
27 */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]28 mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
29 POGO_E02_OE_VAL_HIGH,
30 POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]31
32 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]33 static const u32 kwmpp_config[] = {
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]34 MPP0_NF_IO2,
35 MPP1_NF_IO3,
36 MPP2_NF_IO4,
37 MPP3_NF_IO5,
38 MPP4_NF_IO6,
39 MPP5_NF_IO7,
40 MPP6_SYSRST_OUTn,
41 MPP7_GPO,
42 MPP8_UART0_RTS,
43 MPP9_UART0_CTS,
44 MPP10_UART0_TXD,
45 MPP11_UART0_RXD,
46 MPP12_SD_CLK,
47 MPP13_SD_CMD,
48 MPP14_SD_D0,
49 MPP15_SD_D1,
50 MPP16_SD_D2,
51 MPP17_SD_D3,
52 MPP18_NF_IO0,
53 MPP19_NF_IO1,
54 MPP29_TSMP9, /* USB Power Enable */
55 MPP48_GPIO, /* LED green */
56 MPP49_GPIO, /* LED orange */
57 0
58 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]59 kirkwood_mpp_conf(kwmpp_config, NULL);
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]60 return 0;
61}
62
63int board_init(void)
64{
65 /* Boot parameters address */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]66 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]67
68 return 0;
69}
70
71#ifdef CONFIG_RESET_PHY_R
72/* Configure and initialize PHY */
73void reset_phy(void)
74{
75 u16 reg;
76 u16 devadr;
77 char *name = "egiga0";
78
79 if (miiphy_set_current_dev(name))
80 return;
81
82 /* command to read PHY dev address */
83 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
84 printf("Err..(%s) could not read PHY dev address\n", __func__);
85 return;
86 }
87
88 /*
89 * Enable RGMII delay on Tx and Rx for CPU port
90 * Ref: sec 4.7.2 of chip datasheet
91 */
92 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
93 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
94 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
95 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
96 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
97
98 /* reset the phy */
99 miiphy_reset(name, devadr);
100
101 debug("88E1116 Initialized on %s\n", name);
102}
103#endif /* CONFIG_RESET_PHY_R */