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git01.mediatek.com / filogic / uboot / 4c8b286967166cb7ac8db3033692ae89680a445c / . / arch / arm / include / asm / arch-mx7 / mx7d_rdc.h
blob: 9073cbddc307b82578d5f7b757ec7ec2fa36733b [file] [log] [blame]
Peng Fanac57efa2016-01-28 16:55:02 +0800[diff] [blame]1/*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __MX7D_RDC_H__
8#define __MX7D_RDC_H__
9
10#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */
11
12enum {
13 RDC_PER_GPIO1 = 0,
14 RDC_PER_GPIO2,
15 RDC_PER_GPIO3,
16 RDC_PER_GPIO4,
17 RDC_PER_GPIO5,
18 RDC_PER_GPIO6,
19 RDC_PER_GPIO7,
20 RDC_PER_IOMUXC_LPSR_GPR,
21 RDC_PER_WDOG1,
22 RDC_PER_WDOG2,
23 RDC_PER_WDOG3,
24 RDC_PER_WDOG4,
25 RDC_PER_IOMUXC_LPSR,
26 RDC_PER_GPT1,
27 RDC_PER_GPT2,
28 RDC_PER_GPT3,
29 RDC_PER_GPT4,
30 RDC_PER_ROMCP,
31 RDC_PER_KPP,
32 RDC_PER_IOMUXC,
33 RDC_PER_IOMUXCGPR,
34 RDC_PER_OCOTP,
35 RDC_PER_ANATOP_DIG,
36 RDC_PER_SNVS_HP,
37 RDC_PER_CCM,
38 RDC_PER_SRC,
39 RDC_PER_GPC,
40 RDC_PER_SEMA1,
41 RDC_PER_SEMA2,
42 RDC_PER_RDC,
43 RDC_PER_CSU,
44 RDC_PER_RESERVED1,
45 RDC_PER_RESERVED2,
46 RDC_PER_ADC1,
47 RDC_PER_ADC2,
48 RDC_PER_ECSPI4,
49 RDC_PER_FLEX_TIMER1,
50 RDC_PER_FLEX_TIMER2,
51 RDC_PER_PWM1,
52 RDC_PER_PWM2,
53 RDC_PER_PWM3,
54 RDC_PER_PWM4,
55 RDC_PER_SYSTEM_COUNTER_READ,
56 RDC_PER_SYSTEM_COUNTER_COMPARE,
57 RDC_PER_SYSTEM_COUNTER_CONTROL,
58 RDC_PER_PCIE_PHY,
59 RDC_PER_RESERVED3,
60 RDC_PER_EPDC,
61 RDC_PER_PXP,
62 RDC_PER_CSI,
63 RDC_PER_RESERVED4,
64 RDC_PER_LCDIF,
65 RDC_PER_RESERVED5,
66 RDC_PER_MIPI_CSI,
67 RDC_PER_MIPI_DSI,
68 RDC_PER_RESERVED6,
69 RDC_PER_TZASC,
70 RDC_PER_DDR_PHY,
71 RDC_PER_DDRC,
72 RDC_PER_RESERVED7,
73 RDC_PER_PERFMON1,
74 RDC_PER_PERFMON2,
75 RDC_PER_AXI_DEBUG_MON,
76 RDC_PER_QOSC,
77 RDC_PER_FLEXCAN1,
78 RDC_PER_FLEXCAN2,
79 RDC_PER_I2C1,
80 RDC_PER_I2C2,
81 RDC_PER_I2C3,
82 RDC_PER_I2C4,
83 RDC_PER_UART4,
84 RDC_PER_UART5,
85 RDC_PER_UART6,
86 RDC_PER_UART7,
87 RDC_PER_MU_A,
88 RDC_PER_MU_B,
89 RDC_PER_SEMAPHORE_HS,
90 RDC_PER_USB_PL301,
91 RDC_PER_RESERVED8,
92 RDC_PER_RESERVED9,
93 RDC_PER_RESERVED10,
94 RDC_PER_USB1,
95 RDC_PER_USB2,
96 RDC_PER_USB3,
97 RDC_PER_USDHC1,
98 RDC_PER_USDHC2,
99 RDC_PER_USDHC3,
100 RDC_PER_RESERVED11,
101 RDC_PER_RESERVED12,
102 RDC_PER_SIM1,
103 RDC_PER_SIM2,
104 RDC_PER_QSPI,
105 RDC_PER_WEIM,
106 RDC_PER_SDMA,
107 RDC_PER_ENET1,
108 RDC_PER_ENET2,
109 RDC_PER_RESERVED13,
110 RDC_PER_RESERVED14,
111 RDC_PER_ECSPI1,
112 RDC_PER_ECSPI2,
113 RDC_PER_ECSPI3,
114 RDC_PER_RESERVED15,
115 RDC_PER_UART1,
116 RDC_PER_UART2,
117 RDC_PER_UART3,
118 RDC_PER_RESERVED16,
119 RDC_PER_SAI1,
120 RDC_PER_SAI2,
121 RDC_PER_SAI3,
122 RDC_PER_RESERVED17,
123 RDC_PER_RESERVED18,
124 RDC_PER_SPBA,
125 RDC_PER_DAP,
126 RDC_PER_RESERVED19,
127 RDC_PER_RESERVED20,
128 RDC_PER_RESERVED21,
129 RDC_PER_CAAM,
130 RDC_PER_RESERVED22,
131};
132
133enum {
134 RDC_MA_A7 = 0,
135 RDC_MA_M4,
136 RDC_MA_PCIE,
137 RDC_MA_CSI,
138 RDC_MA_EPDC,
139 RDC_MA_LCDIF,
140 RDC_MA_DISPLAY_PORT,
141 RDC_MA_PXP,
142 RDC_MA_CORESIGHT,
143 RDC_MA_DAP,
144 RDC_MA_CAAM,
145 RDC_MA_SDMA_PERI,
146 RDC_MA_SDMA_BURST,
147 RDC_MA_APBHDMA,
148 RDC_MA_RAWNAND,
149 RDC_MA_USDHC1,
150 RDC_MA_USDHC2,
151 RDC_MA_USDHC3,
152 RDC_MA_NC1,
153 RDC_MA_USB,
154 RDC_MA_NC2,
155 RDC_MA_TEST,
156 RDC_MA_ENET1_TX,
157 RDC_MA_ENET1_RX,
158 RDC_MA_ENET2_TX,
159 RDC_MA_ENET2_RX,
160 RDC_MA_SDMA,
161};
162
163#endif /* __MX7D_RDC_H__*/