| Patrick Delaunay | 4c6fcbc | 2024-01-15 15:05:57 +0100 | [diff] [blame^] | 1 | if STM32MP15X |
| Patrick Delaunay | ff45fca | 2022-05-20 18:24:44 +0200 | [diff] [blame] | 2 | |
| Patrick Delaunay | 4c6fcbc | 2024-01-15 15:05:57 +0100 | [diff] [blame^] | 3 | config STM32MP15X_STM32IMAGE |
| Patrick Delaunay | ff45fca | 2022-05-20 18:24:44 +0200 | [diff] [blame] | 4 | bool "Support STM32 image for generated U-Boot image" |
| 5 | depends on TFABOOT |
| 6 | help |
| 7 | Support of STM32 image generation for SOC STM32MP15x |
| 8 | for TF-A boot when FIP container is not used |
| 9 | |
| 10 | choice |
| 11 | prompt "STM32MP15x board select" |
| 12 | optional |
| 13 | |
| Patrick Delaunay | 4c6fcbc | 2024-01-15 15:05:57 +0100 | [diff] [blame^] | 14 | config TARGET_ST_STM32MP15X |
| Patrick Delaunay | ff45fca | 2022-05-20 18:24:44 +0200 | [diff] [blame] | 15 | bool "STMicroelectronics STM32MP15x boards" |
| 16 | imply BOOTSTAGE |
| 17 | imply CMD_BOOTSTAGE |
| 18 | imply CMD_CLS if CMD_BMP |
| 19 | imply DISABLE_CONSOLE |
| 20 | imply PRE_CONSOLE_BUFFER |
| 21 | imply SILENT_CONSOLE |
| 22 | help |
| 23 | target the STMicroelectronics board with SOC STM32MP15x |
| 24 | managed by board/st/stm32mp1: |
| 25 | Evalulation board (EV1) or Discovery board (DK1 and DK2). |
| 26 | The difference between board are managed with devicetree |
| 27 | |
| 28 | config TARGET_DH_STM32MP1_PDK2 |
| 29 | bool "DH STM32MP1 PDK2" |
| 30 | help |
| 31 | Target the DH PDK2 development kit with STM32MP15x SoM. |
| 32 | |
| 33 | config TARGET_MICROGEA_STM32MP1 |
| 34 | bool "Engicam MicroGEA STM32MP1 SOM" |
| 35 | imply BOOTSTAGE |
| 36 | imply CMD_BOOTSTAGE |
| 37 | imply CMD_CLS if CMD_BMP |
| 38 | imply DISABLE_CONSOLE |
| 39 | imply PRE_CONSOLE_BUFFER |
| 40 | imply SILENT_CONSOLE |
| 41 | help |
| 42 | MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. |
| 43 | |
| 44 | MicroGEA STM32MP1 MicroDev 2.0: |
| 45 | * MicroDev 2.0 is a general purpose miniature carrier board with CAN, |
| 46 | LTE and LVDS panel interfaces. |
| 47 | * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board |
| 48 | for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. |
| 49 | |
| 50 | MicroGEA STM32MP1 MicroDev 2.0 7" OF: |
| 51 | * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS |
| 52 | panel and toucscreen. |
| 53 | * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with |
| 54 | pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" |
| 55 | Open Frame Solution board. |
| 56 | |
| 57 | config TARGET_ICORE_STM32MP1 |
| 58 | bool "Engicam i.Core STM32MP1 SOM" |
| 59 | imply BOOTSTAGE |
| 60 | imply CMD_BOOTSTAGE |
| 61 | imply CMD_CLS if CMD_BMP |
| 62 | imply DISABLE_CONSOLE |
| 63 | imply PRE_CONSOLE_BUFFER |
| 64 | imply SILENT_CONSOLE |
| 65 | help |
| 66 | i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A. |
| 67 | |
| 68 | i.Core STM32MP1 EDIMM2.2: |
| 69 | * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. |
| 70 | * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for |
| 71 | creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. |
| 72 | |
| 73 | i.Core STM32MP1 C.TOUCH 2.0 |
| 74 | * C.TOUCH 2.0 is a general purpose Carrier board. |
| 75 | * i.Core STM32MP1 needs to mount on top of this Carrier board |
| 76 | for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. |
| 77 | |
| 78 | endchoice |
| 79 | |
| Patrick Delaunay | 2d2ff64 | 2022-05-20 18:24:45 +0200 | [diff] [blame] | 80 | config STM32MP15_PWR |
| 81 | bool "Enable driver for STM32MP15x PWR" |
| 82 | depends on DM_REGULATOR && DM_PMIC |
| 83 | default y |
| 84 | help |
| 85 | This config enables implementation of driver-model pmic and |
| 86 | regulator uclass features for access to STM32MP15x PWR. |
| 87 | |
| 88 | config SPL_STM32MP15_PWR |
| 89 | bool "Enable driver for STM32MP15x PWR in SPL" |
| 90 | depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC |
| 91 | default y |
| 92 | help |
| 93 | This config enables implementation of driver-model pmic and |
| 94 | regulator uclass features for access to STM32MP15x PWR in SPL. |
| 95 | |
| Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 96 | config TEXT_BASE |
| Patrick Delaunay | ff45fca | 2022-05-20 18:24:44 +0200 | [diff] [blame] | 97 | default 0xC0100000 |
| 98 | |
| 99 | config PRE_CON_BUF_ADDR |
| 100 | default 0xC02FF000 |
| 101 | |
| 102 | config PRE_CON_BUF_SZ |
| 103 | default 4096 |
| 104 | |
| 105 | config BOOTSTAGE_STASH_ADDR |
| 106 | default 0xC3000000 |
| 107 | |
| 108 | if BOOTCOUNT_GENERIC |
| 109 | config SYS_BOOTCOUNT_SINGLEWORD |
| 110 | default y |
| 111 | |
| 112 | # TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) |
| 113 | config SYS_BOOTCOUNT_ADDR |
| 114 | default 0x5C00A154 |
| 115 | endif |
| 116 | |
| 117 | if DEBUG_UART |
| 118 | |
| 119 | config DEBUG_UART_BOARD_INIT |
| Patrick Delaunay | 00202f7 | 2022-10-11 16:44:26 +0200 | [diff] [blame] | 120 | default y if SPL |
| Patrick Delaunay | ff45fca | 2022-05-20 18:24:44 +0200 | [diff] [blame] | 121 | |
| 122 | # debug on UART4 by default |
| 123 | config DEBUG_UART_BASE |
| 124 | default 0x40010000 |
| 125 | |
| 126 | # clock source is HSI on reset |
| 127 | config DEBUG_UART_CLOCK |
| 128 | default 64000000 |
| 129 | endif |
| 130 | |
| 131 | source "board/st/stm32mp1/Kconfig" |
| 132 | source "board/dhelectronics/dh_stm32mp1/Kconfig" |
| 133 | source "board/engicam/stm32mp1/Kconfig" |
| 134 | |
| 135 | endif |