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git01.mediatek.com / filogic / uboot / 4c3808765ff74ec6fbaa0867683a3365812256ec / . / arch / arm / dts / imx8qm-rom7720-a1.dts
blob: 5f9ac955ed4c6256c8894442ed58fd9f617d515d [file] [log] [blame]
Oliver Grautedafcd992019-09-20 07:08:41 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017 NXP
5 */
6
7/dts-v1/;
8
9/* First 128KB is for PSCI ATF. */
10/memreserve/ 0x80000000 0x00020000;
11
12#include "fsl-imx8qm.dtsi"
13
14/ {
15 model = "Advantech iMX8QM Qseven series";
16 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
17
18 chosen {
19 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
20 stdout-path = &lpuart0;
21 };
22
23 leds {
24 compatible = "gpio-leds";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_gpio_leds>;
27 user {
28 label = "heartbeat";
29 gpios = <&gpio2 15 0>;
30 default-state = "on";
31 linux,default-trigger = "heartbeat";
32 };
33 };
34
35 regulators {
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 reg_usb_otg1_vbus: regulator@0 {
41 compatible = "regulator-fixed";
42 reg = <0>;
43 regulator-name = "usb_otg1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
47 enable-active-high;
48 };
49
50 reg_usdhc2_vmmc: usdhc2_vmmc {
51 compatible = "regulator-fixed";
52 regulator-name = "sw-3p3-sd1";
53 regulator-min-microvolt = <3300000>;
54 regulator-max-microvolt = <3300000>;
55 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
56 enable-active-high;
57 };
58 };
59};
60
61&iomuxc {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_hog_1>;
64
65 imx8qm-mek {
66 pinctrl_hog_1: hoggrp-1 {
67 fsl,pins = <
68 SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048
69 >;
70 };
71
72 pinctrl_fec1: fec1grp {
73 fsl,pins = <
74 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
75 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048
76 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
77 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
78 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
79 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
80 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
81 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
82 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
83 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
84 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
85 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
86 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
87 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
88 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
89 >;
90 };
91
92 pinctrl_fec2: fec2grp {
93 fsl,pins = <
94 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
95 SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
96 SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
97 SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
98 SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
99 SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
100 SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
101 SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
102 SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
103 SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
104 SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
105 SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
106 SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
107 >;
108 };
109
110 pinctrl_lpuart0: lpuart0grp {
111 fsl,pins = <
112 SC_P_UART0_RX_DMA_UART0_RX 0x06000020
113 SC_P_UART0_TX_DMA_UART0_TX 0x06000020
114 >;
115 };
116
117 pinctrl_usdhc1: usdhc1grp {
118 fsl,pins = <
119 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
120 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
121 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
122 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
123 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
124 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
125 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
126 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
127 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
128 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
129 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
130 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
131 >;
132 };
133
134 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
135 fsl,pins = <
136 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
137 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
138 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
139 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
140 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
141 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
142 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
143 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
144 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
145 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
146 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
147 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
148 >;
149 };
150
151 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
152 fsl,pins = <
153 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
154 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
155 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
156 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
157 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
158 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
159 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
160 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
161 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
162 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
163 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
164 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
165 >;
166 };
167
168 pinctrl_usdhc2_gpio: usdhc2grpgpio {
169 fsl,pins = <
170 SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
171 SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
172 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
173 >;
174 };
175
176 pinctrl_usdhc2: usdhc2grp {
177 fsl,pins = <
178 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
179 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
180 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
181 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
182 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
183 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
184 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
185 >;
186 };
187
188 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
189 fsl,pins = <
190 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
191 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
192 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
193 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
194 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
195 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
196 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
197 >;
198 };
199
200 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
201 fsl,pins = <
202 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
203 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
204 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
205 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
206 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
207 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
208 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
209 >;
210 };
211
212 pinctrl_usdhc3: usdhc3grp {
213 fsl,pins = <
214 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
215 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
216 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
217 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
218 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
219 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
220 /* WP */
221 SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021
222 /* CD */
223 SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
224 >;
225 };
226
227 pinctrl_lpi2c1: lpi2c1grp {
228 fsl,pins = <
229 SC_P_GPT0_CLK_DMA_I2C1_SCL 0x06000020
230 SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x06000020
231 /*
232 * Change the default alt function from SCL/SDA to others,
233 * to avoid select input conflict with GPT0
234 */
235 SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0700004c
236 SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0700004c
237 SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0700004c
238 SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0700004c
239 >;
240 };
241
242 pinctrl_gpio_leds: gpioledsgrp {
243 fsl,pins = <
244 SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
245 >;
246 };
247 };
248};
249
250&gpio2 {
251 status = "okay";
252};
253
254&gpio4 {
255 status = "okay";
256};
257
258&gpio5 {
259 status = "okay";
260};
261
262&usdhc1 {
263 pinctrl-names = "default", "state_100mhz", "state_200mhz";
264 pinctrl-0 = <&pinctrl_usdhc1>;
265 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
266 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
267 bus-width = <8>;
268 non-removable;
269 status = "okay";
270};
271
272&usdhc2 {
273 pinctrl-names = "default", "state_100mhz", "state_200mhz";
274 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
275 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
276 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
277 bus-width = <4>;
278 cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
279 wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
280 vmmc-supply = <&reg_usdhc2_vmmc>;
281 status = "okay";
282};
283
284&usdhc3 {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_usdhc3>;
287 bus-width = <4>;
288 cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
289 wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
290 status = "okay";
291};
292
293&fec1 {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_fec1>;
296 phy-mode = "rgmii";
297 phy-handle = <&ethphy0>;
298 fsl,ar8031-phy-fixup;
299 fsl,magic-packet;
300 status = "okay";
301
302 mdio {
303 #address-cells = <1>;
304 #size-cells = <0>;
305
306 ethphy0: ethernet-phy@0 {
307 compatible = "ethernet-phy-ieee802.3-c22";
308 reg = <0>;
309 };
310
311 ethphy1: ethernet-phy@1 {
312 compatible = "ethernet-phy-ieee802.3-c22";
313 reg = <1>;
314 };
315 };
316};
317
318&fec2 {
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_fec2>;
321 phy-mode = "rgmii";
322 phy-handle = <&ethphy1>;
323 fsl,ar8031-phy-fixup;
324 fsl,magic-packet;
325 status = "okay";
326};
327
328&i2c1 {
329 #address-cells = <1>;
330 #size-cells = <0>;
331 clock-frequency = <100000>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_lpi2c1>;
334 status = "okay";
335
336 pca9557_a: gpio@18 {
337 compatible = "nxp,pca9557";
338 reg = <0x18>;
339 gpio-controller;
340 #gpio-cells = <2>;
341 };
342
343 pca9557_b: gpio@19 {
344 compatible = "nxp,pca9557";
345 reg = <0x19>;
346 gpio-controller;
347 #gpio-cells = <2>;
348 };
349
350 pca9557_c: gpio@1b {
351 compatible = "nxp,pca9557";
352 reg = <0x1b>;
353 gpio-controller;
354 #gpio-cells = <2>;
355 };
356
357 pca9557_d: gpio@1f {
358 compatible = "nxp,pca9557";
359 reg = <0x1f>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 };
363};
364
365&lpuart0 {
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_lpuart0>;
368 status = "okay";
369};
370
371&lpuart1 {
372 status = "okay";
373};