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git01.mediatek.com / filogic / uboot / 4c3808765ff74ec6fbaa0867683a3365812256ec / . / arch / arm / dts / fsl-ls2081a-rdb.dts
blob: b0b7ef08a021823728f9b6f420a6afef4993854b [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]2/*
3 * NXP LS2081A RDB board device tree source for QSPI-boot
4 *
5 * Author: Priyanka Jain <priyanka.jain@nxp.com>
6 *
7 * Copyright 2017 NXP
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]8 */
9
10/dts-v1/;
11
12#include "fsl-ls2080a.dtsi"
13
14/ {
15 model = "Freescale Layerscape 2081a RDB Board";
16 compatible = "fsl,ls2081a-rdb", "fsl,ls2080a";
17
18 aliases {
19 spi0 = &qspi;
20 spi1 = &dspi;
21 };
22};
23
24&dspi {
25 bus-num = <0>;
26 status = "okay";
27
28 dflash0: n25q512a {
29 #address-cells = <1>;
30 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]31 compatible = "jedec,spi-nor";
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]32 spi-max-frequency = <3000000>;
33 spi-cpol;
34 spi-cpha;
35 reg = <0>;
36 };
37};
38
39&qspi {
40 bus-num = <0>;
41 status = "okay";
42
Santan Kumar31e6bfb2017-08-18 15:20:32 +0530[diff] [blame]43 qflash0: s25fs512s@0 {
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]44 #address-cells = <1>;
45 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]46 compatible = "jedec,spi-nor";
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]47 spi-max-frequency = <50000000>;
48 reg = <0>;
49 };
50
Santan Kumar31e6bfb2017-08-18 15:20:32 +0530[diff] [blame]51 qflash1: s25fs512s@1 {
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]52 #address-cells = <1>;
53 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]54 compatible = "jedec,spi-nor";
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]55 spi-max-frequency = <50000000>;
56 reg = <1>;
57 };
58};