blob: e5a5d7532c9a918f0d08634fa09d1603b3e4eec8 [file] [log] [blame]
Marek Vasutde0a6bf2011-11-08 23:18:09 +00001/*
2 * Freescale i.MX28 SSP MMC driver
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
9 * Terry Lv
10 *
11 * Copyright 2007, Freescale Semiconductor, Inc
12 * Andy Fleming
13 *
14 * Based vaguely on the pxa mmc code:
15 * (C) Copyright 2003
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
17 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020018 * SPDX-License-Identifier: GPL-2.0+
Marek Vasutde0a6bf2011-11-08 23:18:09 +000019 */
20#include <common.h>
21#include <malloc.h>
22#include <mmc.h>
23#include <asm/errno.h>
24#include <asm/io.h>
25#include <asm/arch/clock.h>
26#include <asm/arch/imx-regs.h>
27#include <asm/arch/sys_proto.h>
Stefan Roese136f3f42013-04-09 21:06:07 +000028#include <asm/imx-common/dma.h>
Marek Vasutacc8d6b2012-08-26 15:19:07 +000029#include <bouncebuf.h>
Marek Vasutde0a6bf2011-11-08 23:18:09 +000030
31struct mxsmmc_priv {
32 int id;
Otavio Salvador22f4ff92012-08-05 09:05:31 +000033 struct mxs_ssp_regs *regs;
Marek Vasutde0a6bf2011-11-08 23:18:09 +000034 uint32_t buswidth;
35 int (*mmc_is_wp)(int);
Marek Vasut722181e2013-01-22 15:01:03 +000036 int (*mmc_cd)(int);
Marek Vasut5796bed2012-03-15 18:33:21 +000037 struct mxs_dma_desc *desc;
Marek Vasutde0a6bf2011-11-08 23:18:09 +000038};
39
40#define MXSMMC_MAX_TIMEOUT 10000
Marek Vasut97c04d62012-07-06 21:25:56 +000041#define MXSMMC_SMALL_TRANSFER 512
Marek Vasutde0a6bf2011-11-08 23:18:09 +000042
Marek Vasut722181e2013-01-22 15:01:03 +000043static int mxsmmc_cd(struct mxsmmc_priv *priv)
44{
45 struct mxs_ssp_regs *ssp_regs = priv->regs;
46
47 if (priv->mmc_cd)
48 return priv->mmc_cd(priv->id);
49
50 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
51}
52
Marek Vasut92af6152012-07-06 21:25:55 +000053static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
54{
55 struct mxs_ssp_regs *ssp_regs = priv->regs;
56 uint32_t *data_ptr;
57 int timeout = MXSMMC_MAX_TIMEOUT;
58 uint32_t reg;
59 uint32_t data_count = data->blocksize * data->blocks;
60
61 if (data->flags & MMC_DATA_READ) {
62 data_ptr = (uint32_t *)data->dest;
63 while (data_count && --timeout) {
64 reg = readl(&ssp_regs->hw_ssp_status);
65 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
66 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
67 data_count -= 4;
68 timeout = MXSMMC_MAX_TIMEOUT;
69 } else
70 udelay(1000);
71 }
72 } else {
73 data_ptr = (uint32_t *)data->src;
74 timeout *= 100;
75 while (data_count && --timeout) {
76 reg = readl(&ssp_regs->hw_ssp_status);
77 if (!(reg & SSP_STATUS_FIFO_FULL)) {
78 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
79 data_count -= 4;
80 timeout = MXSMMC_MAX_TIMEOUT;
81 } else
82 udelay(1000);
83 }
84 }
85
86 return timeout ? 0 : COMM_ERR;
87}
Marek Vasut97c04d62012-07-06 21:25:56 +000088
Marek Vasut92af6152012-07-06 21:25:55 +000089static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
90{
91 uint32_t data_count = data->blocksize * data->blocks;
Marek Vasut92af6152012-07-06 21:25:55 +000092 int dmach;
Marek Vasut042cfd62012-07-06 21:25:57 +000093 struct mxs_dma_desc *desc = priv->desc;
Stephen Warren4a8629e2012-11-06 11:27:29 +000094 void *addr;
95 unsigned int flags;
96 struct bounce_buffer bbstate;
Marek Vasut042cfd62012-07-06 21:25:57 +000097
98 memset(desc, 0, sizeof(struct mxs_dma_desc));
99 desc->address = (dma_addr_t)desc;
Marek Vasut92af6152012-07-06 21:25:55 +0000100
Marek Vasut92af6152012-07-06 21:25:55 +0000101 if (data->flags & MMC_DATA_READ) {
102 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
Marek Vasutacc8d6b2012-08-26 15:19:07 +0000103 addr = data->dest;
104 flags = GEN_BB_WRITE;
Marek Vasut92af6152012-07-06 21:25:55 +0000105 } else {
106 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
Marek Vasutacc8d6b2012-08-26 15:19:07 +0000107 addr = (void *)data->src;
108 flags = GEN_BB_READ;
109 }
110
Stephen Warren4a8629e2012-11-06 11:27:29 +0000111 bounce_buffer_start(&bbstate, addr, data_count, flags);
Marek Vasutacc8d6b2012-08-26 15:19:07 +0000112
Stephen Warren4a8629e2012-11-06 11:27:29 +0000113 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
Marek Vasut761fb5b2012-08-31 16:18:10 +0000114
Marek Vasut92af6152012-07-06 21:25:55 +0000115 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
116 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
117
Marek Vasuteadf3372013-02-23 02:42:58 +0000118 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
Marek Vasut92af6152012-07-06 21:25:55 +0000119 mxs_dma_desc_append(dmach, priv->desc);
Marek Vasutacc8d6b2012-08-26 15:19:07 +0000120 if (mxs_dma_go(dmach)) {
Stephen Warren4a8629e2012-11-06 11:27:29 +0000121 bounce_buffer_stop(&bbstate);
Marek Vasut92af6152012-07-06 21:25:55 +0000122 return COMM_ERR;
Marek Vasutacc8d6b2012-08-26 15:19:07 +0000123 }
Marek Vasut92af6152012-07-06 21:25:55 +0000124
Stephen Warren4a8629e2012-11-06 11:27:29 +0000125 bounce_buffer_stop(&bbstate);
Marek Vasutacc8d6b2012-08-26 15:19:07 +0000126
Marek Vasut92af6152012-07-06 21:25:55 +0000127 return 0;
128}
Marek Vasut92af6152012-07-06 21:25:55 +0000129
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000130/*
131 * Sends a command out on the bus. Takes the mmc pointer,
132 * a command pointer, and an optional data pointer.
133 */
134static int
135mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
136{
137 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000138 struct mxs_ssp_regs *ssp_regs = priv->regs;
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000139 uint32_t reg;
140 int timeout;
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000141 uint32_t ctrl0;
Marek Vasut92af6152012-07-06 21:25:55 +0000142 int ret;
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000143
144 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
145
146 /* Check bus busy */
147 timeout = MXSMMC_MAX_TIMEOUT;
148 while (--timeout) {
149 udelay(1000);
150 reg = readl(&ssp_regs->hw_ssp_status);
151 if (!(reg &
152 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
153 SSP_STATUS_CMD_BUSY))) {
154 break;
155 }
156 }
157
158 if (!timeout) {
159 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
160 return TIMEOUT;
161 }
162
163 /* See if card is present */
Marek Vasut722181e2013-01-22 15:01:03 +0000164 if (!mxsmmc_cd(priv)) {
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000165 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
166 return NO_CARD_ERR;
167 }
168
169 /* Start building CTRL0 contents */
170 ctrl0 = priv->buswidth;
171
172 /* Set up command */
173 if (!(cmd->resp_type & MMC_RSP_CRC))
174 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
175 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
176 ctrl0 |= SSP_CTRL0_GET_RESP;
177 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
178 ctrl0 |= SSP_CTRL0_LONG_RESP;
179
Marek Vasut042cfd62012-07-06 21:25:57 +0000180 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
181 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
182 else
183 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
184
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000185 /* Command index */
186 reg = readl(&ssp_regs->hw_ssp_cmd0);
187 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
188 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
189 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
190 reg |= SSP_CMD0_APPEND_8CYC;
191 writel(reg, &ssp_regs->hw_ssp_cmd0);
192
193 /* Command argument */
194 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
195
196 /* Set up data */
197 if (data) {
198 /* READ or WRITE */
199 if (data->flags & MMC_DATA_READ) {
200 ctrl0 |= SSP_CTRL0_READ;
Marek Vasut336ff282012-05-01 11:09:52 +0000201 } else if (priv->mmc_is_wp &&
202 priv->mmc_is_wp(mmc->block_dev.dev)) {
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000203 printf("MMC%d: Can not write a locked card!\n",
204 mmc->block_dev.dev);
205 return UNUSABLE_ERR;
206 }
207
208 ctrl0 |= SSP_CTRL0_DATA_XFER;
Marek Vasutecf843e2013-01-22 15:01:04 +0000209
210 reg = data->blocksize * data->blocks;
211#if defined(CONFIG_MX23)
212 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
213
214 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
215 SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
216 ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
217 ((ffs(data->blocksize) - 1) <<
218 SSP_CMD0_BLOCK_SIZE_OFFSET));
219#elif defined(CONFIG_MX28)
220 writel(reg, &ssp_regs->hw_ssp_xfer_size);
221
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000222 reg = ((data->blocks - 1) <<
223 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
224 ((ffs(data->blocksize) - 1) <<
225 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
226 writel(reg, &ssp_regs->hw_ssp_block_size);
Marek Vasutecf843e2013-01-22 15:01:04 +0000227#endif
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000228 }
229
230 /* Kick off the command */
231 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
232 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
233
234 /* Wait for the command to complete */
235 timeout = MXSMMC_MAX_TIMEOUT;
236 while (--timeout) {
237 udelay(1000);
238 reg = readl(&ssp_regs->hw_ssp_status);
239 if (!(reg & SSP_STATUS_CMD_BUSY))
240 break;
241 }
242
243 if (!timeout) {
244 printf("MMC%d: Command %d busy\n",
245 mmc->block_dev.dev, cmd->cmdidx);
246 return TIMEOUT;
247 }
248
249 /* Check command timeout */
250 if (reg & SSP_STATUS_RESP_TIMEOUT) {
251 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
252 mmc->block_dev.dev, cmd->cmdidx, reg);
253 return TIMEOUT;
254 }
255
256 /* Check command errors */
257 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
258 printf("MMC%d: Command %d error (status 0x%08x)!\n",
259 mmc->block_dev.dev, cmd->cmdidx, reg);
260 return COMM_ERR;
261 }
262
263 /* Copy response to response buffer */
264 if (cmd->resp_type & MMC_RSP_136) {
265 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
266 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
267 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
268 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
269 } else
270 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
271
272 /* Return if no data to process */
273 if (!data)
274 return 0;
275
Marek Vasut97c04d62012-07-06 21:25:56 +0000276 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
Marek Vasut97c04d62012-07-06 21:25:56 +0000277 ret = mxsmmc_send_cmd_pio(priv, data);
278 if (ret) {
279 printf("MMC%d: Data timeout with command %d "
280 "(status 0x%08x)!\n",
281 mmc->block_dev.dev, cmd->cmdidx, reg);
282 return ret;
283 }
Marek Vasut042cfd62012-07-06 21:25:57 +0000284 } else {
285 ret = mxsmmc_send_cmd_dma(priv, data);
286 if (ret) {
287 printf("MMC%d: DMA transfer failed\n",
288 mmc->block_dev.dev);
289 return ret;
290 }
Marek Vasutdac199b2012-04-05 03:30:35 +0000291 }
Marek Vasut5796bed2012-03-15 18:33:21 +0000292
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000293 /* Check data errors */
294 reg = readl(&ssp_regs->hw_ssp_status);
295 if (reg &
296 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
297 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
298 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
299 mmc->block_dev.dev, cmd->cmdidx, reg);
300 return COMM_ERR;
301 }
302
303 return 0;
304}
305
306static void mxsmmc_set_ios(struct mmc *mmc)
307{
308 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000309 struct mxs_ssp_regs *ssp_regs = priv->regs;
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000310
311 /* Set the clock speed */
312 if (mmc->clock)
Otavio Salvador2906f942013-01-11 03:19:03 +0000313 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000314
315 switch (mmc->bus_width) {
316 case 1:
317 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
318 break;
319 case 4:
320 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
321 break;
322 case 8:
323 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
324 break;
325 }
326
327 /* Set the bus width */
328 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
329 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
330
331 debug("MMC%d: Set %d bits bus width\n",
332 mmc->block_dev.dev, mmc->bus_width);
333}
334
335static int mxsmmc_init(struct mmc *mmc)
336{
337 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000338 struct mxs_ssp_regs *ssp_regs = priv->regs;
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000339
340 /* Reset SSP */
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000341 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000342
Otavio Salvador254f2972013-01-22 15:01:02 +0000343 /* Reconfigure the SSP block for MMC operation */
344 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
345 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
346 SSP_CTRL1_DMA_ENABLE |
347 SSP_CTRL1_POLARITY |
348 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
349 SSP_CTRL1_DATA_CRC_IRQ_EN |
350 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
351 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
352 SSP_CTRL1_RESP_ERR_IRQ_EN,
353 &ssp_regs->hw_ssp_ctrl1_set);
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000354
355 /* Set initial bit clock 400 KHz */
Otavio Salvador2906f942013-01-11 03:19:03 +0000356 mxs_set_ssp_busclock(priv->id, 400);
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000357
358 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
359 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
360 udelay(200);
361 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
362
363 return 0;
364}
365
Marek Vasut722181e2013-01-22 15:01:03 +0000366int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000367{
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000368 struct mmc *mmc = NULL;
369 struct mxsmmc_priv *priv = NULL;
Marek Vasut93541b42012-04-08 17:34:46 +0000370 int ret;
Marek Vasuteadf3372013-02-23 02:42:58 +0000371 const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
Marek Vasut3b46aa22013-01-11 03:19:14 +0000372
Marek Vasuteadf3372013-02-23 02:42:58 +0000373 if (!mxs_ssp_bus_id_valid(id))
Marek Vasut3b46aa22013-01-11 03:19:14 +0000374 return -ENODEV;
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000375
376 mmc = malloc(sizeof(struct mmc));
377 if (!mmc)
378 return -ENOMEM;
379
380 priv = malloc(sizeof(struct mxsmmc_priv));
381 if (!priv) {
382 free(mmc);
383 return -ENOMEM;
384 }
385
Marek Vasut5796bed2012-03-15 18:33:21 +0000386 priv->desc = mxs_dma_desc_alloc();
387 if (!priv->desc) {
388 free(priv);
389 free(mmc);
390 return -ENOMEM;
391 }
392
Marek Vasuteadf3372013-02-23 02:42:58 +0000393 ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
Marek Vasut93541b42012-04-08 17:34:46 +0000394 if (ret)
395 return ret;
396
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000397 priv->mmc_is_wp = wp;
Marek Vasut722181e2013-01-22 15:01:03 +0000398 priv->mmc_cd = cd;
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000399 priv->id = id;
Marek Vasut96026612013-01-11 03:19:02 +0000400 priv->regs = mxs_ssp_regs_by_bus(id);
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000401
402 sprintf(mmc->name, "MXS MMC");
403 mmc->send_cmd = mxsmmc_send_cmd;
404 mmc->set_ios = mxsmmc_set_ios;
405 mmc->init = mxsmmc_init;
Thierry Redingb9c8b772012-01-02 01:15:37 +0000406 mmc->getcd = NULL;
Nikita Kiryanov020f2612012-12-03 02:19:46 +0000407 mmc->getwp = NULL;
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000408 mmc->priv = priv;
409
410 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
411
412 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
413 MMC_MODE_HS_52MHz | MMC_MODE_HS;
414
415 /*
416 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
417 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
418 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
419 * CLOCK_RATE could be any integer from 0 to 255.
420 */
421 mmc->f_min = 400000;
Marek Vasut3b46aa22013-01-11 03:19:14 +0000422 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
Marek Vasut67f38972012-04-08 18:50:18 +0000423 mmc->b_max = 0x20;
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000424
425 mmc_register(mmc);
426 return 0;
427}