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git01.mediatek.com / filogic / uboot / 4c08a1d337c3a9905a6bc28f589c010e22b10d32 / . / board / ait / cam_enc_4xx / u-boot-spl.lds
blob: fdfbfc38a96769bb805105be4bd2fa0225156518 [file] [log] [blame]
Heiko Schocher6c1b1192011-11-01 20:00:35 +0000[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
4 *
5 * (C) Copyright 2008
6 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher6c1b1192011-11-01 20:00:35 +0000[diff] [blame]9 */
10
11MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
Albert ARIBAUDfd2c9812013-04-12 05:14:31 +0000[diff] [blame]12 LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
Heiko Schocher6c1b1192011-11-01 20:00:35 +0000[diff] [blame]13
14OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
15OUTPUT_ARCH(arm)
16ENTRY(_start)
17SECTIONS
18{
Heiko Schocherb22c74b2012-03-07 04:10:00 +0000[diff] [blame]19 . = CONFIG_SPL_TEXT_BASE;
Heiko Schocher6c1b1192011-11-01 20:00:35 +0000[diff] [blame]20
21 . = ALIGN(4);
22 .text :
23 {
24 __start = .;
Benoît Thébaudeau3954db82013-04-11 09:36:03 +0000[diff] [blame]25 arch/arm/cpu/arm926ejs/start.o (.text*)
Heiko Schocher6c1b1192011-11-01 20:00:35 +0000[diff] [blame]26 *(.text*)
27 } >.sram
28
29 . = ALIGN(4);
30 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
31
32 . = ALIGN(4);
33 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
34 . = ALIGN(4);
Heiko Schocher6c1b1192011-11-01 20:00:35 +0000[diff] [blame]35 .rel.dyn : {
36 __rel_dyn_start = .;
37 *(.rel*)
38 __rel_dyn_end = .;
39 } >.sram
40
Heiko Schocher6c1b1192011-11-01 20:00:35 +0000[diff] [blame]41 .bss :
42 {
43 . = ALIGN(4);
44 __bss_start = .;
45 *(.bss*)
46 . = ALIGN(4);
Simon Glassed70c8f2013-03-14 06:54:53 +0000[diff] [blame]47 __bss_end = .;
Heiko Schocher6c1b1192011-11-01 20:00:35 +0000[diff] [blame]48 } >.sram
49
50 __image_copy_end = .;
51 _end = .;
52}