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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roesebf5ed2e2015-11-18 11:06:09 +01002/*
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
Stefan Roesebf5ed2e2015-11-18 11:06:09 +01004 */
5#ifndef __CONFIG_SOCFPGA_SR1500_H__
6#define __CONFIG_SOCFPGA_SR1500_H__
7
8#include <asm/arch/base_addr_ac5.h>
9
Stefan Roesebf5ed2e2015-11-18 11:06:09 +010010/* Memory configurations */
11#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
12
13/* Booting Linux */
Stefan Roesebf5ed2e2015-11-18 11:06:09 +010014#define CONFIG_LOADADDR 0x01000000
15#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
Stefan Roesebf5ed2e2015-11-18 11:06:09 +010016
17/* Ethernet on SoC (EMAC) */
18#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
19/* The PHY is autodetected, so no MII PHY address is needed here */
Stefan Roesebf5ed2e2015-11-18 11:06:09 +010020#define PHY_ANEG_TIMEOUT 8000
21
Stefan Roesebf5ed2e2015-11-18 11:06:09 +010022/* Enable SPI NOR flash reset, needed for SPI booting */
23#define CONFIG_SPI_N25Q256A_RESET
24
25/*
26 * Bootcounter
27 */
Stefan Roesebf5ed2e2015-11-18 11:06:09 +010028#define CONFIG_SYS_BOOTCOUNT_BE
29
Stefan Roesebf5ed2e2015-11-18 11:06:09 +010030/* Environment setting for SPI flash */
Stefan Roesebf5ed2e2015-11-18 11:06:09 +010031#define CONFIG_ENV_SECT_SIZE (64 * 1024)
32#define CONFIG_ENV_SIZE (16 * 1024)
Stefan Roese85e84392016-03-03 16:57:39 +010033#define CONFIG_ENV_OFFSET 0x000e0000
Stefan Roesebf5ed2e2015-11-18 11:06:09 +010034#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
Stefan Roese85e84392016-03-03 16:57:39 +010035
Marek Vasut4003fe22016-02-26 19:11:30 +010036/* The rest of the configuration is shared */
37#include <configs/socfpga_common.h>
38
Stefan Roesebf5ed2e2015-11-18 11:06:09 +010039#endif /* __CONFIG_SOCFPGA_SR1500_H__ */