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Dinh Nguyenad51f7c2012-10-04 06:46:02 +00001/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Dinh Nguyenad51f7c2012-10-04 06:46:02 +00005 */
6
7#include <config.h>
Dinh Nguyenad51f7c2012-10-04 06:46:02 +00008
Dinh Nguyenad51f7c2012-10-04 06:46:02 +00009/* Set up the platform, once the cpu has been initialized */
10.globl lowlevel_init
11lowlevel_init:
12
13 /* Remap */
14#ifdef CONFIG_SPL_BUILD
15 /*
16 * SPL : configure the remap (L3 NIC-301 GPV)
17 * so the on-chip RAM at lower memory instead ROM.
18 */
19 ldr r0, =SOCFPGA_L3REGS_ADDRESS
20 mov r1, #0x19
21 str r1, [r0]
22#else
23 /*
24 * U-Boot : configure the remap (L3 NIC-301 GPV)
25 * so the SDRAM at lower memory instead on-chip RAM.
26 */
27 ldr r0, =SOCFPGA_L3REGS_ADDRESS
28 mov r1, #0x2
29 str r1, [r0]
30
31 /* Private components security */
32
33 /*
34 * U-Boot : configure private timer, global timer and cpu
35 * component access as non secure for kernel stage (as required
36 * by kernel)
37 */
38 mrc p15,4,r0,c15,c0,0
39 add r1, r0, #0x54
40 ldr r2, [r1]
41 orr r2, r2, #0xff
42 orr r2, r2, #0xf00
43 str r2, [r1]
44#endif /* #ifdef CONFIG_SPL_BUILD */
45 mov pc, lr