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git01.mediatek.com / filogic / uboot / 118ad85969207d7f1e89a6ef27cc70c10e70b82e / . / arch / arm / dts / imx8ulp.dtsi
blob: d3b16bd2feb493dbb2d7dd56b63736018fd13ee4 [file] [log] [blame]
Peng Fan28ed72c2021-08-07 16:01:12 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2021 NXP
4 */
5
6#include <dt-bindings/clock/imx8ulp-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include "imx8ulp-pinfunc.h"
10
11/ {
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 aliases {
17 gpio0 = &gpiod;
18 gpio1 = &gpioe;
19 gpio2 = &gpiof;
20 serial0 = &lpuart5;
21 mmc0 = &usdhc0;
22 mmc1 = &usdhc1;
23 mmc2 = &usdhc2;
24 spi0 = &flexspi0;
25 spi2 = &flexspi2;
26 ethernet0 = &fec;
27 i2c7 = &lpi2c7;
28 usbphy0 = &usbphy0;
29 usb0 = &usbotg0;
30 usbphy1 = &usbphy1;
31 usb1 = &usbotg1;
32 };
33
34 cpus: cpus {
35 #address-cells = <2>;
36 #size-cells = <0>;
37
38 idle-states {
39 entry-method = "psci";
40
41 CPU_SLEEP: cpu-sleep {
42 compatible = "arm,idle-state";
43 arm,psci-suspend-param = <0x0010033>;
44 local-timer-stop;
45 entry-latency-us = <1000>;
46 exit-latency-us = <700>;
47 min-residency-us = <2700>;
48 wakeup-latency-us = <1500>;
49 };
50 };
51
52 /* We have 1 clusters with 4 Cortex-A35 cores */
53 A35_0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a35";
56 reg = <0x0 0x0>;
57 enable-method = "psci";
58 next-level-cache = <&A35_L2>;
59 clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>;
60 };
61
62 A35_1: cpu@1 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a35";
65 reg = <0x0 0x1>;
66 enable-method = "psci";
67 next-level-cache = <&A35_L2>;
68 clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>;
69 };
70
71 A35_L2: l2-cache0 {
72 compatible = "cache";
73 };
74 };
75
76 a35_opp_table: opp-table {
77 compatible = "operating-points-v2";
78 opp-shared;
79
80 opp-504000000 {
81 opp-hz = /bits/ 64 <504000000>;
82 opp-microvolt = <800000>;
83 clock-latency-ns = <150000>;
84 };
85
86 opp-744000000 {
87 opp-hz = /bits/ 64 <744000000>;
88 opp-microvolt = <900000>;
89 clock-latency-ns = <150000>;
90 };
91
92 opp-1008000000 {
93 opp-hz = /bits/ 64 <1008000000>;
94 opp-microvolt = <1000000>;
95 clock-latency-ns = <150000>;
96 opp-suspend;
97 };
98 };
99
100 s400_mu: mu@27020000 {
101 u-boot,dm-spl;
102 compatible = "fsl,imx8ulp-mu";
103 reg = <0 0x27020000 0 0x10000>;
104 status = "okay";
105 };
106
107 gic: interrupt-controller@2d400000 {
108 compatible = "arm,gic-v3";
109 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
110 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
111 #interrupt-cells = <3>;
112 interrupt-controller;
113 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
114 };
115
116 psci {
117 compatible = "arm,psci-1.0";
118 method = "smc";
119 };
120
121 timer {
122 compatible = "arm,armv8-timer";
123 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
124 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
125 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
126 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
127 };
128
129 frosc: clock-frosc {
130 compatible = "fixed-clock";
131 clock-frequency = <192000000>;
132 clock-output-names = "frosc";
133 #clock-cells = <0>;
134 };
135
136 lposc: clock-lposc {
137 compatible = "fixed-clock";
138 clock-frequency = <1000000>;
139 clock-output-names = "lposc";
140 #clock-cells = <0>;
141 };
142
143 rosc: clock-rosc {
144 compatible = "fixed-clock";
145 clock-frequency = <32768>;
146 clock-output-names = "rosc";
147 #clock-cells = <0>;
148 };
149
150 sosc: clock-sosc {
151 compatible = "fixed-clock";
152 clock-frequency = <24000000>;
153 clock-output-names = "sosc";
154 #clock-cells = <0>;
155 };
156
157 sram@0x2201f000 {
158 compatible = "mmio-sram";
159 reg = <0x0 0x2201f000 0x0 0x1000>;
160
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges = <0 0x0 0x2201f000 0x1000>;
164
165 /* TODO: split or unify */
166 scmi_pd: scmi_pd@0 {
167 compatible = "arm,scmi-shmem";
168 reg = <0x0 0x200>;
169 };
170 };
171
172 firmware {
173 scmi {
174 compatible = "arm,scmi-smc";
175 arm,smc-id = <0xc20000fe>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 shmem = <&scmi_pd>;
179
180 scmi_devpd: protocol@11 {
181 reg = <0x11>;
182 #power-domain-cells = <1>;
183 };
184
185 scmi_perf: protocol@13 {
186 reg = <0x13>;
187 };
188 };
189 };
190
191 soc@0 {
192 compatible = "simple-bus";
193 #address-cells = <1>;
194 #size-cells = <1>;
195 ranges = <0x0 0x0 0x0 0x80000000>;
196
197 per_bridge0: bus@28000000 {
198 compatible = "simple-bus";
199 reg = <0x28000000 0x800000>;
200 #address-cells = <1>;
201 #size-cells = <1>;
202 ranges;
203
204 flexspi0: flexspi@28039000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "nxp,imx8ulp-fspi";
208 reg = <0x28039000 0x10000>,
209 <0x04000000 0x7ffffff>;
210 reg-names = "fspi_base", "fspi_mmap";
211 status = "disabled";
212 };
213 };
214
215 per_bridge3: bus@29000000 {
216 compatible = "simple-bus";
217 reg = <0x29000000 0x800000>;
218 #address-cells = <1>;
219 #size-cells = <1>;
220 ranges;
221
222 edma1: dma-controller@29010000 {
223 compatible = "fsl,imx8ulp-edma";
224 reg = <0x29010000 0x10000>,
225 <0x29020000 0x10000>, <0x29030000 0x10000>,
226 <0x29040000 0x10000>, <0x29050000 0x10000>,
227 <0x29060000 0x10000>, <0x29070000 0x10000>,
228 <0x29080000 0x10000>, <0x29090000 0x10000>,
229 <0x290a0000 0x10000>, <0x290b0000 0x10000>,
230 <0x290c0000 0x10000>, <0x290d0000 0x10000>,
231 <0x290e0000 0x10000>, <0x290f0000 0x10000>,
232 <0x29100000 0x10000>, <0x29110000 0x10000>,
233 <0x29120000 0x10000>, <0x29130000 0x10000>,
234 <0x29140000 0x10000>, <0x29150000 0x10000>,
235 <0x29160000 0x10000>, <0x29170000 0x10000>,
236 <0x29180000 0x10000>, <0x29190000 0x10000>,
237 <0x291a0000 0x10000>, <0x291b0000 0x10000>,
238 <0x291c0000 0x10000>, <0x291d0000 0x10000>,
239 <0x291e0000 0x10000>, <0x291f0000 0x10000>,
240 <0x29200000 0x10000>, <0x29210000 0x10000>;
241 #dma-cells = <3>;
242 dma-channels = <32>;
243 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx",
276 "edma1-chan2-tx", "edma1-chan3-tx",
277 "edma1-chan4-tx", "edma1-chan5-tx",
278 "edma1-chan6-tx", "edma1-chan7-tx",
279 "edma1-chan8-tx", "edma1-chan9-tx",
280 "edma1-chan10-tx", "edma1-chan11-tx",
281 "edma1-chan12-tx", "edma1-chan13-tx",
282 "edma1-chan14-tx", "edma1-chan15-tx",
283 "edma1-chan16-tx", "edma1-chan17-tx",
284 "edma1-chan18-tx", "edma1-chan19-tx",
285 "edma1-chan20-tx", "edma1-chan21-tx",
286 "edma1-chan22-tx", "edma1-chan23-tx",
287 "edma1-chan24-tx", "edma1-chan25-tx",
288 "edma1-chan26-tx", "edma1-chan27-tx",
289 "edma1-chan28-tx", "edma1-chan29-tx",
290 "edma1-chan30-tx", "edma1-chan31-tx";
291 clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>,
292 <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>,
293 <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>,
294 <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>,
295 <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>,
296 <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>,
297 <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>,
298 <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>,
299 <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>,
300 <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>,
301 <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>,
302 <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>,
303 <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>,
304 <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>,
305 <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>,
306 <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>,
307 <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>;
308 clock-names = "edma-mp-clk",
309 "edma1-chan0-clk", "edma1-chan1-clk",
310 "edma1-chan2-clk", "edma1-chan3-clk",
311 "edma1-chan4-clk", "edma1-chan5-clk",
312 "edma1-chan6-clk", "edma1-chan7-clk",
313 "edma1-chan8-clk", "edma1-chan9-clk",
314 "edma1-chan10-clk", "edma1-chan11-clk",
315 "edma1-chan12-clk", "edma1-chan13-clk",
316 "edma1-chan14-clk", "edma1-chan15-clk",
317 "edma1-chan16-clk", "edma1-chan17-clk",
318 "edma1-chan18-clk", "edma1-chan19-clk",
319 "edma1-chan20-clk", "edma1-chan21-clk",
320 "edma1-chan22-clk", "edma1-chan23-clk",
321 "edma1-chan24-clk", "edma1-chan25-clk",
322 "edma1-chan26-clk", "edma1-chan27-clk",
323 "edma1-chan28-clk", "edma1-chan29-clk",
324 "edma1-chan30-clk", "edma1-chan31-clk";
325 status = "okay";
326 };
327
328 wdog3: watchdog@292a0000 {
329 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
330 reg = <0x292a0000 0x10000>;
331 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
333 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
334 assigned-clocks-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
335 timeout-sec = <40>;
336 };
337
338 cgc1: clock-controller@292c0000 {
339 compatible = "fsl,imx8ulp-cgc1";
340 reg = <0x292c0000 0x10000>;
341 clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
342 clock-names = "rosc", "sosc", "frosc", "lposc";
343 #clock-cells = <1>;
344 };
345
346 pcc3: clock-controller@292d0000 {
347 compatible = "fsl,imx8ulp-pcc3";
348 reg = <0x292d0000 0x10000>;
349 #clock-cells = <1>;
350 };
351
352 tpm5: tpm@29340000 {
353 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
354 reg = <0x29340000 0x1000>;
355 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
357 <&pcc3 IMX8ULP_CLK_TPM5>;
358 clock-names = "ipg", "per";
359 };
360
361 lpuart4: serial@29390000 {
362 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
363 reg = <0x29390000 0x1000>;
364 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
366 clock-names = "ipg";
367 status = "disabled";
368 };
369
370 lpuart5: serial@293a0000 {
371 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
372 reg = <0x293a0000 0x1000>;
373 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
374 clock-names = "ipg";
375 status = "disabled";
376 };
377 };
378
379 per_bridge4: bus@29800000 {
380 compatible = "simple-bus";
381 reg = <0x29800000 0x800000>;
382 #address-cells = <1>;
383 #size-cells = <1>;
384 ranges;
385
386 pcc4: clock-controller@29800000 {
387 compatible = "fsl,imx8ulp-pcc4";
388 reg = <0x29800000 0x10000>;
389 #clock-cells = <1>;
390 };
391
392 lpi2c6: lpi2c6@29840000 {
393 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
394 reg = <0x29840000 0x10000>;
395 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
397 <&pcc4 IMX8ULP_CLK_LPI2C6>;
398 clock-names = "per", "ipg";
399 status = "disabled";
400 };
401
402 lpi2c7: lpi2c7@29850000 {
403 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
404 reg = <0x29850000 0x10000>;
405 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
407 <&pcc4 IMX8ULP_CLK_LPI2C7>;
408 clock-names = "per", "ipg";
409 status = "disabled";
410 };
411
412 flexspi2: flexspi@29810000 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 compatible = "nxp,imx8ulp-fspi";
416 reg = <0x29810000 0x10000>,
417 <0x60000000 0xfffffff>;
418 reg-names = "fspi_base", "fspi_mmap";
419 status = "disabled";
420 };
421
422 flexspi2_nand: flexspi2_nand@29810000 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "fsl,imx8-fspi-nand";
426 reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
427 reg-names = "FlexSPI", "FlexSPI-memory";
428 status = "disabled";
429 };
430
431 iomuxc1: pinctrl@298c0000 {
432 compatible = "fsl,imx8ulp-iomuxc1";
433 reg = <0x298c0000 0x10000>;
434 fsl,mux_mask = <0xf00>;
435 };
436
437 usdhc0: mmc@298d0000 {
438 compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc";
439 reg = <0x298d0000 0x10000>;
440 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&cgc1 IMX8ULP_CLK_DUMMY>,
442 <&cgc1 IMX8ULP_CLK_DUMMY>,
443 <&pcc4 IMX8ULP_CLK_USDHC0>;
444 clock-names = "ipg", "ahb", "per";
445 fsl,tuning-start-tap = <20>;
446 fsl,tuning-step= <2>;
447 bus-width = <4>;
448 status = "disabled";
449 };
450
451 usdhc1: mmc@298e0000 {
452 compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc";
453 reg = <0x298e0000 0x10000>;
454 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cgc1 IMX8ULP_CLK_DUMMY>,
456 <&cgc1 IMX8ULP_CLK_DUMMY>,
457 <&pcc4 IMX8ULP_CLK_USDHC1>;
458 clock-names = "ipg", "ahb", "per";
459 fsl,tuning-start-tap = <20>;
460 fsl,tuning-step= <2>;
461 bus-width = <4>;
462 status = "disabled";
463 };
464
465 usdhc2: mmc@298f0000 {
466 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
467 reg = <0x298f0000 0x10000>;
468 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
470 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
471 <&pcc4 IMX8ULP_CLK_USDHC2>;
472 clock-names = "ipg", "ahb", "per";
473 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC2>;
474 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>;
475 assigned-clock-rates = <396000000>, <396000000>;
476 fsl,tuning-start-tap = <20>;
477 fsl,tuning-step= <2>;
478 bus-width = <4>;
479 status = "disabled";
480 };
481
482 usbotg0: usb@29900000 {
483 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
484 "fsl,imx27-usb";
485 reg = <0x29900000 0x200>;
486 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&pcc4 IMX8ULP_CLK_USB0>;
488 fsl,usbphy = <&usbphy0>;
489 fsl,usbmisc = <&usbmisc0 0>;
490 ahb-burst-config = <0x0>;
491 tx-burst-size-dword = <0x8>;
492 rx-burst-size-dword = <0x8>;
493 status = "disabled";
494 };
495
496 usbmisc0: usbmisc@29900200 {
497 #index-cells = <1>;
498 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
499 "fsl,imx6q-usbmisc";
500 reg = <0x29900200 0x200>;
501 };
502
503 usbphy0: usbphy@29910000 {
504 compatible = "fsl,imx8ulp-usbphy",
505 "fsl,imx7ulp-usbphy", "fsl,imx23-usbphy";
506 reg = <0x29910000 0x1000>;
507 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
509 };
510
511 usbotg1: usb@29920000 {
512 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
513 "fsl,imx27-usb";
514 reg = <0x29920000 0x200>;
515 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&pcc4 IMX8ULP_CLK_USB1>;
517 fsl,usbphy = <&usbphy1>;
518 fsl,usbmisc = <&usbmisc1 0>;
519 ahb-burst-config = <0x0>;
520 tx-burst-size-dword = <0x8>;
521 rx-burst-size-dword = <0x8>;
522 status = "disabled";
523 };
524
525 usbmisc1: usbmisc@29920200 {
526 #index-cells = <1>;
527 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
528 "fsl,imx6q-usbmisc";
529 reg = <0x29920200 0x200>;
530 };
531
532 usbphy1: usbphy@29930000 {
533 compatible = "fsl,imx8ulp-usbphy",
534 "fsl,imx7ulp-usbphy", "fsl,imx23-usbphy";
535 reg = <0x29930000 0x1000>;
536 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
538 };
539
540 fec: ethernet@29950000 {
541 compatible = "fsl,imx8ulp-fec", "fsl,imx6sx-fec";
542 reg = <0x29950000 0x10000>;
543 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&pcc4 IMX8ULP_CLK_ENET>,
545 <&pcc4 IMX8ULP_CLK_ENET>,
546 <&cgc1 IMX8ULP_CLK_ENETSTAMP_SEL>,
547 <&pcc4 IMX8ULP_CLK_ENET>,
548 <&pcc4 IMX8ULP_CLK_ENET>;
549 clock-names = "ipg", "ahb", "ptp",
550 "enet_clk_ref", "enet_out";
551 fsl,num-tx-queues = <3>;
552 fsl,num-rx-queues = <3>;
553 status = "disabled";
554 };
555
556 };
557
558 gpioe: gpio@2d000000 {
559 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
560 reg = <0x2d000080 0x1000 0x2d000040 0x40>;
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
564 interrupt-controller;
565 #interrupt-cells = <2>;
566 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
567 <&pcc4 IMX8ULP_CLK_PCTLE>;
568 clock-names = "gpio", "port";
569 gpio-ranges = <&iomuxc1 0 32 24>;
570 };
571
572 gpiof: gpio@2d010000 {
573 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
574 reg = <0x2d010080 0x1000 0x2d010040 0x40>;
575 gpio-controller;
576 #gpio-cells = <2>;
577 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
578 interrupt-controller;
579 #interrupt-cells = <2>;
580 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
581 <&pcc4 IMX8ULP_CLK_PCTLF>;
582 clock-names = "gpio", "port";
583 gpio-ranges = <&iomuxc1 0 64 24>;
584 };
585
586 per_bridge5: bus@2d800000 {
587 compatible = "simple-bus";
588 reg = <0x2d800000 0x800000>;
589 #address-cells = <1>;
590 #size-cells = <1>;
591 ranges;
592
593 edma2: dma-controller@2d800000 {
594 compatible = "fsl,imx8ulp-edma";
595 reg = <0x2d800000 0x10000>,
596 <0x2d810000 0x10000>, <0x2d820000 0x10000>,
597 <0x2d830000 0x10000>, <0x2d840000 0x10000>,
598 <0x2d850000 0x10000>, <0x2d860000 0x10000>,
599 <0x2d870000 0x10000>, <0x2d880000 0x10000>,
600 <0x2d890000 0x10000>, <0x2d8a0000 0x10000>,
601 <0x2d8b0000 0x10000>, <0x2d8c0000 0x10000>,
602 <0x2d8d0000 0x10000>, <0x2d8e0000 0x10000>,
603 <0x2d8f0000 0x10000>, <0x2d900000 0x10000>,
604 <0x2d910000 0x10000>, <0x2d920000 0x10000>,
605 <0x2d930000 0x10000>, <0x2d940000 0x10000>,
606 <0x2d950000 0x10000>, <0x2d960000 0x10000>,
607 <0x2d970000 0x10000>, <0x2d980000 0x10000>,
608 <0x2d990000 0x10000>, <0x2d9a0000 0x10000>,
609 <0x2d9b0000 0x10000>, <0x2d9c0000 0x10000>,
610 <0x2d9d0000 0x10000>, <0x2d9e0000 0x10000>,
611 <0x2d9f0000 0x10000>, <0x2da00000 0x10000>;
612 #dma-cells = <3>;
613 dma-channels = <32>;
614 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
646 interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx",
647 "edma2-chan2-tx", "edma2-chan3-tx",
648 "edma2-chan4-tx", "edma2-chan5-tx",
649 "edma2-chan6-tx", "edma2-chan7-tx",
650 "edma2-chan8-tx", "edma2-chan9-tx",
651 "edma2-chan10-tx", "edma2-chan11-tx",
652 "edma2-chan12-tx", "edma2-chan13-tx",
653 "edma2-chan14-tx", "edma2-chan15-tx",
654 "edma2-chan16-tx", "edma2-chan17-tx",
655 "edma2-chan18-tx", "edma2-chan19-tx",
656 "edma2-chan20-tx", "edma2-chan21-tx",
657 "edma2-chan22-tx", "edma2-chan23-tx",
658 "edma2-chan24-tx", "edma2-chan25-tx",
659 "edma2-chan26-tx", "edma2-chan27-tx",
660 "edma2-chan28-tx", "edma2-chan29-tx",
661 "edma2-chan30-tx", "edma2-chan31-tx";
662 clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>,
663 <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>,
664 <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>,
665 <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>,
666 <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>,
667 <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>,
668 <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>,
669 <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>,
670 <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>,
671 <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>,
672 <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>,
673 <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>,
674 <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>,
675 <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>,
676 <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>,
677 <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>,
678 <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>;
679 clock-names = "edma-mp-clk",
680 "edma2-chan0-clk", "edma2-chan1-clk",
681 "edma2-chan2-clk", "edma2-chan3-clk",
682 "edma2-chan4-clk", "edma2-chan5-clk",
683 "edma2-chan6-clk", "edma2-chan7-clk",
684 "edma2-chan8-clk", "edma2-chan9-clk",
685 "edma2-chan10-clk", "edma2-chan11-clk",
686 "edma2-chan12-clk", "edma2-chan13-clk",
687 "edma2-chan14-clk", "edma2-chan15-clk",
688 "edma2-chan16-clk", "edma2-chan17-clk",
689 "edma2-chan18-clk", "edma2-chan19-clk",
690 "edma2-chan20-clk", "edma2-chan21-clk",
691 "edma2-chan22-clk", "edma2-chan23-clk",
692 "edma2-chan24-clk", "edma2-chan25-clk",
693 "edma2-chan26-clk", "edma2-chan27-clk",
694 "edma2-chan28-clk", "edma2-chan29-clk",
695 "edma2-chan30-clk", "edma2-chan31-clk";
696 status = "okay";
697 };
698
699 cgc2: clock-controller@2da60000 {
700 compatible = "fsl,imx8ulp-cgc2";
701 reg = <0x2da60000 0x10000>;
702 clocks = <&sosc>, <&frosc>;
703 clock-names = "sosc", "frosc";
704 #clock-cells = <1>;
705 };
706
707 pcc5: clock-controller@2da70000 {
708 compatible = "fsl,imx8ulp-pcc5";
709 reg = <0x2da70000 0x10000>;
710 #clock-cells = <1>;
711 };
712 };
713
714 gpiod: gpio@2e200000 {
715 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
716 reg = <0x2e200080 0x1000 0x2e200040 0x40>;
717 gpio-controller;
718 #gpio-cells = <2>;
719 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
720 interrupt-controller;
721 #interrupt-cells = <2>;
722 clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
723 <&pcc5 IMX8ULP_CLK_RGPIOD>;
724 clock-names = "gpio", "port";
725 gpio-ranges = <&iomuxc1 0 0 24>;
726 };
727 };
728};