Blame - drivers/video/nexell/soc/s5pxx18_soc_disptop.h - filogic/uboot

Stefan Bosch

3e05411

2020-07-10 19:07:32 +0200

[diff] [blame]

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/* SPDX-License-Identifier: GPL-2.0+

*

*

* Author: junghyun, kim <jhkim@nexell.co.kr>

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*/

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#ifndef _S5PXX18_SOC_DISPTOP_H_

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#define _S5PXX18_SOC_DISPTOP_H_

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Tom Rini

4b5ed11

2024-05-01 19:31:31 -0600

[diff] [blame^]

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#include <linux/types.h>

Stefan Bosch

3e05411

2020-07-10 19:07:32 +0200

[diff] [blame]

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#include "s5pxx18_soc_disptype.h"

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#define NUMBER_OF_DISPTOP_MODULE 1

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#define PHY_BASEADDR_DISPLAYTOP_MODULE 0xC0100000

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#define PHY_BASEADDR_DISPTOP_LIST \

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{ PHY_BASEADDR_DISPLAYTOP_MODULE }

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#define HDMI_ADDR_OFFSET \

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(((PHY_BASEADDR_DISPLAYTOP_MODULE / 0x00100000) % 2) ? 0x100000 \

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: 0x000000)

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#define OTHER_ADDR_OFFSET \

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(((PHY_BASEADDR_DISPLAYTOP_MODULE / 0x00100000) % 2) ? 0x000000 \

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: 0x100000)

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#define PHY_BASEADDR_DISPLAYTOP_MODULE_OFFSET (OTHER_ADDR_OFFSET + 0x001000)

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#define PHY_BASEADDR_DUALDISPLAY_MODULE \

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(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x002000)

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#define PHY_BASEADDR_RESCONV_MODULE \

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(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x003000)

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#define PHY_BASEADDR_LCDINTERFACE_MODULE \

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(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x004000)

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#define PHY_BASEADDR_HDMI_MODULE (PHY_BASEADDR_DISPLAYTOP_MODULE + 0x000000)

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#define PHY_BASEADDR_LVDS_MODULE \

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(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x00a000)

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#define NUMBER_OF_DUALDISPLAY_MODULE 1

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#define INTNUM_OF_DUALDISPLAY_MODULE_PRIMIRQ \

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INTNUM_OF_DISPLAYTOP_MODULE_DUALDISPLAY_PRIMIRQ

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#define INTNUM_OF_DUALDISPLAY_MODULE_SECONDIRQ \

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INTNUM_OF_DISPLAYTOP_MODULE_DUALDISPLAY_SECONDIRQ

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#define RESETINDEX_OF_DUALDISPLAY_MODULE_I_NRST \

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RESETINDEX_OF_DISPLAYTOP_MODULE_I_DUALDISPLAY_NRST

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#define PADINDEX_OF_DUALDISPLAY_O_NCS \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK

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#define PADINDEX_OF_DUALDISPLAY_O_NRD \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC

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#define PADINDEX_OF_DUALDISPLAY_O_RS \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC

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#define PADINDEX_OF_DUALDISPLAY_O_NWR \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE

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#define PADINDEX_OF_DUALDISPLAY_PADPRIMVCLK \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK

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#define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADN_HSYNC \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC

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#define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADN_VSYNC \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC

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#define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADDE \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE

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#define PADINDEX_OF_DUALDISPLAY_PRIM_0_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_1_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_2_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_3_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_4_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_5_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_6_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_7_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_8_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_9_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_10_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_11_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_12_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_13_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_14_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_15_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_16_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_17_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_18_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_19_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_20_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_21_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_22_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_

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#define PADINDEX_OF_DUALDISPLAY_PRIM_23_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_

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#define PADINDEX_OF_DUALDISPLAY_PADSECONDVCLK \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK

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#define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADN_HSYNC \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC

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#define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADN_VSYNC \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC

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#define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADDE \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE

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#define PADINDEX_OF_DUALDISPLAY_SECOND_0_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_1_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_2_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_3_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_4_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_5_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_6_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_7_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_8_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_9_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_10_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_11_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_12_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_13_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_14_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_15_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_16_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_17_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_18_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_19_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_20_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_21_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_22_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_

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#define PADINDEX_OF_DUALDISPLAY_SECOND_23_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_

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#define NUMBER_OF_RESCONV_MODULE 1

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#define INTNUM_OF_RESCONV_MODULE INTNUM_OF_DISPLAYTOP_MODULE_RESCONV_IRQ

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#define RESETINDEX_OF_RESCONV_MODULE_I_NRST \

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RESETINDEX_OF_DISPLAYTOP_MODULE_I_RESCONV_NRST

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#define RESETINDEX_OF_RESCONV_MODULE RESETINDEX_OF_RESCONV_MODULE_I_NRST

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#define NUMBER_OF_LCDINTERFACE_MODULE 1

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#define RESETINDEX_OF_LCDINTERFACE_MODULE_I_NRST \

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RESETINDEX_OF_DISPLAYTOP_MODULE_I_LCDIF_NRST

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#define PADINDEX_OF_LCDINTERFACE_O_VCLK \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK

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#define PADINDEX_OF_LCDINTERFACE_O_NHSYNC \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC

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#define PADINDEX_OF_LCDINTERFACE_O_NVSYNC \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC

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#define PADINDEX_OF_LCDINTERFACE_O_DE \

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PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE

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#define PADINDEX_OF_LCDINTERFACE_RGB24_0_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_1_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_2_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_3_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_4_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_5_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_6_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_7_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_8_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_9_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_10_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_11_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_12_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_13_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_14_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_15_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_16_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_17_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_18_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_19_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_20_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_21_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_22_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_

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#define PADINDEX_OF_LCDINTERFACE_RGB24_23_ \

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PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_

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#define NUMBER_OF_HDMI_MODULE 1

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#define INTNUM_OF_HDMI_MODULE INTNUM_OF_DISPLAYTOP_MODULE_HDMI_IRQ

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#define RESETINDEX_OF_HDMI_MODULE_I_NRST \

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RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_NRST

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#define RESETINDEX_OF_HDMI_MODULE_I_NRST_VIDEO \

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RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_VIDEO_NRST

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#define RESETINDEX_OF_HDMI_MODULE_I_NRST_SPDIF \

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RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_SPDIF_NRST

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#define RESETINDEX_OF_HDMI_MODULE_I_NRST_TMDS \

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RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_TMDS_NRST

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#define RESETINDEX_OF_HDMI_MODULE_I_NRST_PHY \

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RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_PHY_NRST

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#define PADINDEX_OF_HDMI_I_PHY_CLKI PADINDEX_OF_DISPLAYTOP_I_HDMI_CLKI

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#define PADINDEX_OF_HDMI_O_PHY_CLKO PADINDEX_OF_DISPLAYTOP_O_HDMI_CLKO

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#define PADINDEX_OF_HDMI_IO_PHY_REXT PADINDEX_OF_DISPLAYTOP_IO_HDMI_REXT

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#define PADINDEX_OF_HDMI_O_PHY_TX0P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX0P

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#define PADINDEX_OF_HDMI_O_PHY_TX0N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX0N

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#define PADINDEX_OF_HDMI_O_PHY_TX1P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX1P

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#define PADINDEX_OF_HDMI_O_PHY_TX1N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX1N

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#define PADINDEX_OF_HDMI_O_PHY_TX2P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX2P

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#define PADINDEX_OF_HDMI_O_PHY_TX2N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX2N

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#define PADINDEX_OF_HDMI_O_PHY_TXCP PADINDEX_OF_DISPLAYTOP_O_HDMI_TXCP

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#define PADINDEX_OF_HDMI_O_PHY_TXCN PADINDEX_OF_DISPLAYTOP_O_HDMI_TXCN

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#define PADINDEX_OF_HDMI_I_HOTPLUG PADINDEX_OF_DISPLAYTOP_I_HDMI_HOTPLUG_5V

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#define PADINDEX_OF_HDMI_IO_PAD_CEC PADINDEX_OF_DISPLAYTOP_IO_HDMI_CEC

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#define NUMBER_OF_LVDS_MODULE 1

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#define RESETINDEX_OF_LVDS_MODULE_I_RESETN \

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RESETINDEX_OF_DISPLAYTOP_MODULE_I_LVDS_NRST

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#define RESETINDEX_OF_LVDS_MODULE RESETINDEX_OF_LVDS_MODULE_I_RESETN

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#define PADINDEX_OF_LVDS_TAP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_A

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#define PADINDEX_OF_LVDS_TAN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_A

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#define PADINDEX_OF_LVDS_TBP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_B

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#define PADINDEX_OF_LVDS_TBN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_B

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#define PADINDEX_OF_LVDS_TCP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_C

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#define PADINDEX_OF_LVDS_TCN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_C

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#define PADINDEX_OF_LVDS_TDP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_D

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#define PADINDEX_OF_LVDS_TDN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_D

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#define PADINDEX_OF_LVDS_TCLKP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_CLK

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#define PADINDEX_OF_LVDS_TCLKN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_CLK

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#define PADINDEX_OF_LVDS_ROUT PADINDEX_OF_DISPLAYTOP_LVDS_ROUT

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#define PADINDEX_OF_LVDS_TEP PADINDEX_OF_DISPLAYTOP_LVDS_TXN_E

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#define PADINDEX_OF_LVDS_TEN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_E

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#define NUMBER_OF_DISPTOP_CLKGEN_MODULE 5

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enum disptop_clkgen_module_index {

res_conv_clkgen = 0,

lcdif_clkgen = 1,

to_mipi_clkgen = 2,

to_lvds_clkgen = 3,

hdmi_clkgen = 4,

};

enum disptop_res_conv_iclk_cclk {

res_conv_iclk = 0,

res_conv_cclk = 1,

};

enum disptop_res_conv_oclk {

res_conv_oclk = 1,

};

enum disptop_lcdif_clk {

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lcdif_pixel_clkx_n = 0,

lcdif_pixel_clk = 1,

};

#define HDMI_SPDIF_CLKGEN 2

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#define HDMI_SPDIF_CLKOUT 0

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#define HDMI_I_VCLK_CLKOUT 0

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#define PHY_BASEADDR_DISPTOP_CLKGEN0_MODULE \

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(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x006000)

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#define PHY_BASEADDR_DISPTOP_CLKGEN1_MODULE \

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(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x007000)

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#define PHY_BASEADDR_DISPTOP_CLKGEN2_MODULE \

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(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x005000)

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#define PHY_BASEADDR_DISPTOP_CLKGEN3_MODULE \

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(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x008000)

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#define PHY_BASEADDR_DISPTOP_CLKGEN4_MODULE \

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(PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x009000)

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struct nx_disp_top_register_set {

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u32 resconv_mux_ctrl;

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u32 interconv_mux_ctrl;

u32 mipi_mux_ctrl;

u32 lvds_mux_ctrl;

u32 hdmifixctrl0;

u32 hdmisyncctrl0;

u32 hdmisyncctrl1;

u32 hdmisyncctrl2;

u32 hdmisyncctrl3;

u32 tftmpu_mux;

u32 hdmifieldctrl;

u32 greg0;

u32 greg1;

u32 greg2;

u32 greg3;

u32 greg4;

u32 greg5;

};

int nx_disp_top_initialize(void);

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u32 nx_disp_top_get_number_of_module(void);

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u32 nx_disp_top_get_physical_address(void);

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u32 nx_disp_top_get_size_of_register_set(void);

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void nx_disp_top_set_base_address(void *base_address);

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void *nx_disp_top_get_base_address(void);

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int nx_disp_top_open_module(void);

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int nx_disp_top_close_module(void);

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int nx_disp_top_check_busy(void);

enum mux_index {

primary_mlc = 0,

secondary_mlc = 1,

resolution_conv = 2,

};

enum prim_pad_mux_index {

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padmux_primary_mlc = 0,

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padmux_primary_mpu = 1,

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padmux_secondary_mlc = 2,

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padmux_resolution_conv = 3,

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};

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void nx_disp_top_set_resconvmux(int benb, u32 sel);

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void nx_disp_top_set_hdmimux(int benb, u32 sel);

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void nx_disp_top_set_mipimux(int benb, u32 sel);

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void nx_disp_top_set_lvdsmux(int benb, u32 sel);

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void nx_disp_top_set_primary_mux(u32 sel);

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void nx_disp_top_hdmi_set_vsync_start(u32 sel);

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void nx_disp_top_hdmi_set_vsync_hsstart_end(u32 start, u32 end);

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void nx_disp_top_hdmi_set_hactive_start(u32 sel);

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void nx_disp_top_hdmi_set_hactive_end(u32 sel);

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void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,

366

u32 hsynctoggle, u32 vsyncclr, u32 hsyncclr,

367

u32 field_use, u32 muxsel);

enum padclk_config {

padclk_clk = 0,

padclk_inv_clk = 1,

padclk_reserved_clk = 2,

373

padclk_reserved_inv_clk = 3,

374

padclk_clk_div2_0 = 4,

375

padclk_clk_div2_90 = 5,

376

padclk_clk_div2_180 = 6,

377

padclk_clk_div2_270 = 7,

378

};

379

380

void nx_disp_top_set_padclock(u32 mux_index, u32 padclk_cfg);

381

void nx_disp_top_set_lcdif_enb(int enb);

382

void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,

383

u32 hsynctoggle, u32 vsyncclr, u32 hsyncclr,

384

u32 field_use, u32 muxsel);

385

386

#endif