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Stefan Roese49639682006-08-15 14:22:35 +02001/*
2 * (C) Copyright 2006
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de
4 *
Stefan Roesea1831882006-10-07 11:35:25 +02005 * (C) Copyright 2006
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese49639682006-08-15 14:22:35 +02009 */
10
11#include <common.h>
Stefan Roese49639682006-08-15 14:22:35 +020012
Jon Loeliger145318c2007-07-09 18:38:39 -050013#if defined(CONFIG_CMD_NAND)
Stefan Roese49639682006-08-15 14:22:35 +020014
Stefan Roesea1831882006-10-07 11:35:25 +020015#include <asm/processor.h>
Stefan Roese49639682006-08-15 14:22:35 +020016#include <nand.h>
17
Stefan Roese49639682006-08-15 14:22:35 +020018struct alpr_ndfc_regs {
Stefan Roese2a4a9432006-11-27 14:12:17 +010019 u8 cmd[4];
20 u8 addr_wait;
21 u8 term;
22 u8 dummy;
23 u8 dummy2;
24 u8 data;
Stefan Roese49639682006-08-15 14:22:35 +020025};
26
27static u8 hwctl;
Stefan Roesea1831882006-10-07 11:35:25 +020028static struct alpr_ndfc_regs *alpr_ndfc = NULL;
Stefan Roese49639682006-08-15 14:22:35 +020029
Stefan Roese2a4a9432006-11-27 14:12:17 +010030#define readb(addr) (u8)(*(volatile u8 *)(addr))
31#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
Stefan Roese49639682006-08-15 14:22:35 +020032
Stefan Roese49639682006-08-15 14:22:35 +020033/*
34 * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
35 * the NAND devices. The NDFC has command, address and data registers that
36 * when accessed will set up the NAND flash pins appropriately. We'll use the
37 * hwcontrol function to save the configuration in a global variable.
38 * We can then use this information in the read and write functions to
39 * determine which NDFC register to access.
40 *
Stefan Roesea1831882006-10-07 11:35:25 +020041 * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
Stefan Roese49639682006-08-15 14:22:35 +020042 */
William Juul52c07962007-10-31 13:53:06 +010043static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
William Juulb76ec382007-11-08 10:39:53 +010044{
William Juul9e9c2c12007-11-09 13:32:30 +010045 struct nand_chip *this = mtd->priv;
Stefan Roese49639682006-08-15 14:22:35 +020046
William Juul52c07962007-10-31 13:53:06 +010047 if (ctrl & NAND_CTRL_CHANGE) {
48 if ( ctrl & NAND_CLE )
49 hwctl |= 0x1;
50 else
51 hwctl &= ~0x1;
52 if ( ctrl & NAND_ALE )
53 hwctl |= 0x2;
54 else
55 hwctl &= ~0x2;
56 if ( (ctrl & NAND_NCE) != NAND_NCE)
57 writeb(0x00, &(alpr_ndfc->term));
58 }
59 if (cmd != NAND_CMD_NONE)
60 writeb(cmd, this->IO_ADDR_W);
Stefan Roese49639682006-08-15 14:22:35 +020061}
62
Stefan Roesea1831882006-10-07 11:35:25 +020063static u_char alpr_nand_read_byte(struct mtd_info *mtd)
Stefan Roese49639682006-08-15 14:22:35 +020064{
Stefan Roesea1831882006-10-07 11:35:25 +020065 return readb(&(alpr_ndfc->data));
Stefan Roese49639682006-08-15 14:22:35 +020066}
67
Stefan Roesea1831882006-10-07 11:35:25 +020068static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
Stefan Roese49639682006-08-15 14:22:35 +020069{
Stefan Roesea1831882006-10-07 11:35:25 +020070 struct nand_chip *nand = mtd->priv;
Stefan Roese49639682006-08-15 14:22:35 +020071 int i;
72
Stefan Roese49639682006-08-15 14:22:35 +020073 for (i = 0; i < len; i++) {
74 if (hwctl & 0x1)
Stefan Roesea1831882006-10-07 11:35:25 +020075 /*
76 * IO_ADDR_W used as CMD[i] reg to support multiple NAND
77 * chips.
78 */
79 writeb(buf[i], nand->IO_ADDR_W);
80 else if (hwctl & 0x2)
81 writeb(buf[i], &(alpr_ndfc->addr_wait));
82 else
83 writeb(buf[i], &(alpr_ndfc->data));
Stefan Roese49639682006-08-15 14:22:35 +020084 }
85}
86
Stefan Roesea1831882006-10-07 11:35:25 +020087static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
Stefan Roese49639682006-08-15 14:22:35 +020088{
89 int i;
90
91 for (i = 0; i < len; i++) {
Stefan Roesea1831882006-10-07 11:35:25 +020092 buf[i] = readb(&(alpr_ndfc->data));
Stefan Roese49639682006-08-15 14:22:35 +020093 }
94}
95
Stefan Roesea1831882006-10-07 11:35:25 +020096static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
Stefan Roese49639682006-08-15 14:22:35 +020097{
98 int i;
99
100 for (i = 0; i < len; i++)
Stefan Roesea1831882006-10-07 11:35:25 +0200101 if (buf[i] != readb(&(alpr_ndfc->data)))
Stefan Roese49639682006-08-15 14:22:35 +0200102 return i;
103
104 return 0;
105}
106
Stefan Roesea1831882006-10-07 11:35:25 +0200107static int alpr_nand_dev_ready(struct mtd_info *mtd)
Stefan Roese49639682006-08-15 14:22:35 +0200108{
Stefan Roese49639682006-08-15 14:22:35 +0200109 /*
110 * Blocking read to wait for NAND to be ready
111 */
Wolfgang Denkbfed7be2011-11-29 22:17:44 +0000112 (void)readb(&(alpr_ndfc->addr_wait));
Stefan Roese49639682006-08-15 14:22:35 +0200113
114 /*
115 * Return always true
116 */
117 return 1;
Stefan Roese49639682006-08-15 14:22:35 +0200118}
119
Stefan Roese1d9192f2007-01-06 15:56:13 +0100120int board_nand_init(struct nand_chip *nand)
Stefan Roese49639682006-08-15 14:22:35 +0200121{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122 alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
Stefan Roese49639682006-08-15 14:22:35 +0200123
William Juul52c07962007-10-31 13:53:06 +0100124 nand->ecc.mode = NAND_ECC_SOFT;
Stefan Roese49639682006-08-15 14:22:35 +0200125
Stefan Roese49639682006-08-15 14:22:35 +0200126 /* Reference hardware control function */
William Juul52c07962007-10-31 13:53:06 +0100127 nand->cmd_ctrl = alpr_nand_hwcontrol;
Stefan Roesea1831882006-10-07 11:35:25 +0200128 nand->read_byte = alpr_nand_read_byte;
129 nand->write_buf = alpr_nand_write_buf;
130 nand->read_buf = alpr_nand_read_buf;
131 nand->verify_buf = alpr_nand_verify_buf;
132 nand->dev_ready = alpr_nand_dev_ready;
Stefan Roese1d9192f2007-01-06 15:56:13 +0100133
134 return 0;
Stefan Roese49639682006-08-15 14:22:35 +0200135}
136#endif