Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 4b4ef68fda1f5b7954b55a174d19baf7c8536d9b / . / board / Marvell / sheevaplug / sheevaplug.c
blob: 87e49f417bb7138199fd77d3252c46a200206236 [file] [log] [blame]
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]1/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]7 */
8
9#include <common.h>
10#include <miiphy.h>
Lei Wen298ae912011-10-18 20:11:42 +0530[diff] [blame]11#include <asm/arch/cpu.h>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]12#include <asm/arch/kirkwood.h>
13#include <asm/arch/mpp.h>
14#include "sheevaplug.h"
15
16DECLARE_GLOBAL_DATA_PTR;
17
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]18int board_early_init_f(void)
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]19{
20 /*
21 * default gpio configuration
22 * There are maximum 64 gpios controlled through 2 sets of registers
23 * the below configuration configures mainly initial LED status
24 */
25 kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
26 SHEEVAPLUG_OE_VAL_HIGH,
27 SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
28
29 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]30 static const u32 kwmpp_config[] = {
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]31 MPP0_NF_IO2,
32 MPP1_NF_IO3,
33 MPP2_NF_IO4,
34 MPP3_NF_IO5,
35 MPP4_NF_IO6,
36 MPP5_NF_IO7,
37 MPP6_SYSRST_OUTn,
38 MPP7_GPO,
39 MPP8_UART0_RTS,
40 MPP9_UART0_CTS,
41 MPP10_UART0_TXD,
42 MPP11_UART0_RXD,
43 MPP12_SD_CLK,
44 MPP13_SD_CMD,
45 MPP14_SD_D0,
46 MPP15_SD_D1,
47 MPP16_SD_D2,
48 MPP17_SD_D3,
49 MPP18_NF_IO0,
50 MPP19_NF_IO1,
51 MPP20_GPIO,
52 MPP21_GPIO,
53 MPP22_GPIO,
54 MPP23_GPIO,
55 MPP24_GPIO,
56 MPP25_GPIO,
57 MPP26_GPIO,
58 MPP27_GPIO,
59 MPP28_GPIO,
60 MPP29_TSMP9,
61 MPP30_GPIO,
62 MPP31_GPIO,
63 MPP32_GPIO,
64 MPP33_GPIO,
65 MPP34_GPIO,
66 MPP35_GPIO,
67 MPP36_GPIO,
68 MPP37_GPIO,
69 MPP38_GPIO,
70 MPP39_GPIO,
71 MPP40_GPIO,
72 MPP41_GPIO,
73 MPP42_GPIO,
74 MPP43_GPIO,
75 MPP44_GPIO,
76 MPP45_GPIO,
77 MPP46_GPIO,
78 MPP47_GPIO,
79 MPP48_GPIO,
80 MPP49_GPIO,
81 0
82 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]83 kirkwood_mpp_conf(kwmpp_config, NULL);
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]84 return 0;
85}
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]86
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]87int board_init(void)
88{
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]89 /*
90 * arch number of board
91 */
92 gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
93
94 /* adress of boot parameters */
95 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
96
97 return 0;
98}
99
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]100#ifdef CONFIG_RESET_PHY_R
101/* Configure and enable MV88E1116 PHY */
102void reset_phy(void)
103{
104 u16 reg;
105 u16 devadr;
106 char *name = "egiga0";
107
108 if (miiphy_set_current_dev(name))
109 return;
110
111 /* command to read PHY dev address */
112 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
113 printf("Err..%s could not read PHY dev address\n",
114 __FUNCTION__);
115 return;
116 }
117
118 /*
119 * Enable RGMII delay on Tx and Rx for CPU port
120 * Ref: sec 4.7.2 of chip datasheet
121 */
122 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
123 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
124 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
125 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
126 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
127
128 /* reset the phy */
129 miiphy_reset(name, devadr);
130
131 printf("88E1116 Initialized on %s\n", name);
132}
133#endif /* CONFIG_RESET_PHY_R */