Sonic Zhang | 7a91b9b | 2012-08-16 11:16:02 +0800 | [diff] [blame] | 1 | /* |
| 2 | * serial.h - common serial defines for early debug and serial driver. |
| 3 | * any functions defined here must be always_inline since |
| 4 | * initcode cannot have function calls. |
| 5 | * |
| 6 | * Copyright (c) 2004-2011 Analog Devices Inc. |
| 7 | * |
| 8 | * Licensed under the GPL-2 or later. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __BFIN_CPU_SERIAL4_H__ |
| 12 | #define __BFIN_CPU_SERIAL4_H__ |
| 13 | |
| 14 | #include <asm/mach-common/bits/uart4.h> |
| 15 | |
| 16 | #ifndef __ASSEMBLY__ |
| 17 | |
| 18 | #define MMR_UART(n) _PASTE_UART(n, UART, REVID) |
| 19 | #define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) |
| 20 | |
| 21 | struct bfin_mmr_serial { |
| 22 | u32 revid; |
| 23 | u32 control; |
| 24 | u32 status; |
| 25 | u32 scr; |
| 26 | u32 clock; |
| 27 | u32 emask; |
| 28 | u32 emaskst; |
| 29 | u32 emaskcl; |
| 30 | u32 rbr; |
| 31 | u32 thr; |
| 32 | u32 taip; |
| 33 | u32 tsr; |
| 34 | u32 rsr; |
| 35 | u32 txdiv_cnt; |
| 36 | u32 rxdiv_cnt; |
| 37 | }; |
| 38 | #define uart_lsr_t uint32_t |
| 39 | #define _lsr_read(p) bfin_read(&p->status) |
| 40 | #define _lsr_write(p, v) bfin_write(&p->status, v) |
| 41 | |
| 42 | __attribute__((always_inline)) |
| 43 | static inline void serial_early_do_mach_portmux(char port, int mux_mask, |
| 44 | int mux_func, int port_pin) |
| 45 | { |
| 46 | switch (port) { |
| 47 | case 'D': |
| 48 | bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() & |
| 49 | ~mux_mask) | mux_func); |
| 50 | bfin_write_PORTD_FER_SET(port_pin); |
| 51 | break; |
| 52 | case 'G': |
| 53 | bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & |
| 54 | ~mux_mask) | mux_func); |
| 55 | bfin_write_PORTG_FER_SET(port_pin); |
| 56 | break; |
| 57 | } |
| 58 | } |
| 59 | |
| 60 | __attribute__((always_inline)) |
| 61 | static inline void serial_early_do_portmux(void) |
| 62 | { |
| 63 | #if defined(__ADSPBF60x__) |
| 64 | switch (CONFIG_UART_CONSOLE) { |
| 65 | case 0: |
| 66 | serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK, |
| 67 | PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */ |
| 68 | serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK, |
| 69 | PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */ |
| 70 | break; |
| 71 | case 1: |
| 72 | serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK, |
| 73 | PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */ |
| 74 | serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK, |
| 75 | PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */ |
| 76 | break; |
| 77 | } |
| 78 | #else |
| 79 | # if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) |
| 80 | # error "missing portmux logic for UART" |
| 81 | # endif |
| 82 | #endif |
| 83 | SSYNC(); |
| 84 | } |
| 85 | |
| 86 | __attribute__((always_inline)) |
| 87 | static inline uint32_t uart_sclk(void) |
| 88 | { |
| 89 | #if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL) |
| 90 | /* We cannot use get_sclk() early on as it uses caches in |
| 91 | * external memory |
| 92 | */ |
| 93 | return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV / |
| 94 | CONFIG_SCLK0_DIV; |
| 95 | #else |
| 96 | return get_sclk0(); |
| 97 | #endif |
| 98 | } |
| 99 | |
| 100 | __attribute__((always_inline)) |
| 101 | static inline int uart_init(uint32_t uart_base) |
| 102 | { |
| 103 | /* always enable UART to 8-bit mode */ |
| 104 | bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8); |
| 105 | |
| 106 | SSYNC(); |
| 107 | |
| 108 | return 0; |
| 109 | } |
| 110 | |
| 111 | __attribute__((always_inline)) |
| 112 | static inline int serial_early_init(uint32_t uart_base) |
| 113 | { |
| 114 | /* handle portmux crap on different Blackfins */ |
| 115 | serial_do_portmux(); |
| 116 | |
| 117 | return uart_init(uart_base); |
| 118 | } |
| 119 | |
| 120 | __attribute__((always_inline)) |
| 121 | static inline int serial_early_uninit(uint32_t uart_base) |
| 122 | { |
| 123 | /* disable the UART by clearing UEN */ |
| 124 | bfin_write(&pUART->control, 0); |
| 125 | |
| 126 | return 0; |
| 127 | } |
| 128 | |
| 129 | __attribute__((always_inline)) |
| 130 | static inline int serial_early_enabled(uint32_t uart_base) |
| 131 | { |
| 132 | return bfin_read(&pUART->control) & UEN; |
| 133 | } |
| 134 | |
| 135 | __attribute__((always_inline)) |
| 136 | static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) |
| 137 | { |
| 138 | uint32_t divisor = uart_sclk() / (baud * 16); |
| 139 | |
| 140 | /* Program the divisor to get the baud rate we want */ |
| 141 | bfin_write(&pUART->clock, divisor); |
| 142 | SSYNC(); |
| 143 | } |
| 144 | |
| 145 | __attribute__((always_inline)) |
| 146 | static inline void serial_early_put_div(uint32_t divisor) |
| 147 | { |
| 148 | uint32_t uart_base = UART_BASE; |
| 149 | bfin_write(&pUART->clock, divisor); |
| 150 | } |
| 151 | |
| 152 | __attribute__((always_inline)) |
| 153 | static inline uint32_t serial_early_get_div(void) |
| 154 | { |
| 155 | uint32_t uart_base = UART_BASE; |
| 156 | return bfin_read(&pUART->clock); |
| 157 | } |
| 158 | |
| 159 | #endif |
| 160 | |
| 161 | #endif |