Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 1 | /* |
Wolfgang Denk | fd3166d | 2009-05-16 10:47:42 +0200 | [diff] [blame] | 2 | * (C) Copyright 2007-2009 DENX Software Engineering |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 3 | * |
| 4 | * MPC512x Internal Memory Map |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 7 | * |
| 8 | * Based on the MPC83xx header. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __IMMAP_512x__ |
| 12 | #define __IMMAP_512x__ |
| 13 | |
| 14 | #include <asm/types.h> |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 15 | #if defined(CONFIG_E300) |
| 16 | #include <asm/e300.h> |
| 17 | #endif |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 18 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 19 | /* |
| 20 | * System reset offset (PowerPC standard) |
| 21 | */ |
| 22 | #define EXC_OFF_SYS_RESET 0x0100 |
| 23 | #define _START_OFFSET EXC_OFF_SYS_RESET |
| 24 | |
| 25 | #define SPR_5121E 0x80180000 |
| 26 | |
| 27 | /* |
| 28 | * IMMRBAR - Internal Memory Register Base Address |
| 29 | */ |
| 30 | #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ |
| 31 | #define IMMRBAR 0x0000 /* Register offset to immr */ |
| 32 | #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ |
| 33 | #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) |
| 34 | |
| 35 | |
| 36 | #ifndef __ASSEMBLY__ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 37 | typedef struct law512x { |
| 38 | u32 bar; /* Base Addr Register */ |
| 39 | u32 ar; /* Attributes Register */ |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 40 | } law512x_t; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 41 | |
| 42 | /* |
| 43 | * System configuration registers |
| 44 | */ |
| 45 | typedef struct sysconf512x { |
| 46 | u32 immrbar; /* Internal memory map base address register */ |
| 47 | u8 res0[0x1c]; |
| 48 | u32 lpbaw; /* LP Boot Access Window */ |
| 49 | u32 lpcs0aw; /* LP CS0 Access Window */ |
| 50 | u32 lpcs1aw; /* LP CS1 Access Window */ |
| 51 | u32 lpcs2aw; /* LP CS2 Access Window */ |
| 52 | u32 lpcs3aw; /* LP CS3 Access Window */ |
| 53 | u32 lpcs4aw; /* LP CS4 Access Window */ |
| 54 | u32 lpcs5aw; /* LP CS5 Access Window */ |
| 55 | u32 lpcs6aw; /* LP CS6 Access Window */ |
| 56 | u32 lpcs7aw; /* LP CS7 Access Window */ |
| 57 | u8 res1[0x1c]; |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 58 | law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 59 | u8 res2[0x28]; |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 60 | law512x_t ddrlaw; /* DDR Local Access Window */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 61 | u8 res3[0x18]; |
| 62 | u32 mbxbar; /* MBX Base Address */ |
| 63 | u32 srambar; /* SRAM Base Address */ |
| 64 | u32 nfcbar; /* NFC Base Address */ |
| 65 | u8 res4[0x34]; |
| 66 | u32 spridr; /* System Part and Revision ID Register */ |
| 67 | u32 spcr; /* System Priority Configuration Register */ |
| 68 | u8 res5[0xf8]; |
| 69 | } sysconf512x_t; |
| 70 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 71 | #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ |
| 72 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 73 | /* |
| 74 | * Watch Dog Timer (WDT) Registers |
| 75 | */ |
| 76 | typedef struct wdt512x { |
| 77 | u8 res0[4]; |
| 78 | u32 swcrr; /* System watchdog control register */ |
| 79 | u32 swcnr; /* System watchdog count register */ |
| 80 | u8 res1[2]; |
| 81 | u16 swsrr; /* System watchdog service register */ |
| 82 | u8 res2[0xF0]; |
| 83 | } wdt512x_t; |
| 84 | |
| 85 | /* |
| 86 | * RTC Module Registers |
| 87 | */ |
| 88 | typedef struct rtclk512x { |
| 89 | u8 fixme[0x100]; |
| 90 | } rtclk512x_t; |
| 91 | |
| 92 | /* |
| 93 | * General Purpose Timer |
| 94 | */ |
| 95 | typedef struct gpt512x { |
| 96 | u8 fixme[0x100]; |
| 97 | } gpt512x_t; |
| 98 | |
| 99 | /* |
| 100 | * Integrated Programmable Interrupt Controller |
| 101 | */ |
| 102 | typedef struct ipic512x { |
| 103 | u8 fixme[0x100]; |
| 104 | } ipic512x_t; |
| 105 | |
| 106 | /* |
| 107 | * System Arbiter Registers |
| 108 | */ |
| 109 | typedef struct arbiter512x { |
| 110 | u32 acr; /* Arbiter Configuration Register */ |
| 111 | u32 atr; /* Arbiter Timers Register */ |
| 112 | u32 ater; /* Arbiter Transfer Error Register */ |
| 113 | u32 aer; /* Arbiter Event Register */ |
| 114 | u32 aidr; /* Arbiter Interrupt Definition Register */ |
| 115 | u32 amr; /* Arbiter Mask Register */ |
| 116 | u32 aeatr; /* Arbiter Event Attributes Register */ |
| 117 | u32 aeadr; /* Arbiter Event Address Register */ |
| 118 | u32 aerr; /* Arbiter Event Response Register */ |
| 119 | u8 res1[0xDC]; |
| 120 | } arbiter512x_t; |
| 121 | |
| 122 | /* |
| 123 | * Reset Module |
| 124 | */ |
| 125 | typedef struct reset512x { |
| 126 | u32 rcwl; /* Reset Configuration Word Low Register */ |
| 127 | u32 rcwh; /* Reset Configuration Word High Register */ |
| 128 | u8 res0[8]; |
| 129 | u32 rsr; /* Reset Status Register */ |
| 130 | u32 rmr; /* Reset Mode Register */ |
| 131 | u32 rpr; /* Reset protection Register */ |
| 132 | u32 rcr; /* Reset Control Register */ |
| 133 | u32 rcer; /* Reset Control Enable Register */ |
| 134 | u8 res1[0xDC]; |
| 135 | } reset512x_t; |
| 136 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 137 | /* RSR - Reset Status Register */ |
| 138 | #define RSR_SWSR 0x00002000 /* software soft reset */ |
| 139 | #define RSR_SWHR 0x00001000 /* software hard reset */ |
| 140 | #define RSR_JHRS 0x00000200 /* jtag hreset */ |
| 141 | #define RSR_JSRS 0x00000100 /* jtag sreset status */ |
| 142 | #define RSR_CSHR 0x00000010 /* checkstop reset status */ |
| 143 | #define RSR_SWRS 0x00000008 /* software watchdog reset status */ |
| 144 | #define RSR_BMRS 0x00000004 /* bus monitop reset status */ |
| 145 | #define RSR_SRS 0x00000002 /* soft reset status */ |
| 146 | #define RSR_HRS 0x00000001 /* hard reset status */ |
| 147 | #define RSR_RES ~(RSR_SWSR | RSR_SWHR |\ |
| 148 | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ |
| 149 | RSR_BMRS | RSR_SRS | RSR_HRS) |
| 150 | |
| 151 | /* RMR - Reset Mode Register */ |
| 152 | #define RMR_CSRE 0x00000001 /* checkstop reset enable */ |
| 153 | #define RMR_CSRE_SHIFT 0 |
| 154 | #define RMR_RES (~(RMR_CSRE)) |
| 155 | |
| 156 | /* RCR - Reset Control Register */ |
| 157 | #define RCR_SWHR 0x00000002 /* software hard reset */ |
| 158 | #define RCR_SWSR 0x00000001 /* software soft reset */ |
| 159 | #define RCR_RES (~(RCR_SWHR | RCR_SWSR)) |
| 160 | |
| 161 | /* RCER - Reset Control Enable Register */ |
| 162 | #define RCER_CRE 0x00000001 /* software hard reset */ |
| 163 | #define RCER_RES (~(RCER_CRE)) |
| 164 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 165 | /* |
| 166 | * Clock Module |
| 167 | */ |
| 168 | typedef struct clk512x { |
| 169 | u32 spmr; /* System PLL Mode Register */ |
| 170 | u32 sccr[2]; /* System Clock Control Registers */ |
| 171 | u32 scfr[2]; /* System Clock Frequency Registers */ |
| 172 | u8 res0[4]; |
| 173 | u32 bcr; /* Bread Crumb Register */ |
| 174 | u32 pscccr[12]; /* PSC0-11 Clock Control Registers */ |
Wolfgang Denk | d616a92 | 2009-06-14 20:58:45 +0200 | [diff] [blame] | 175 | u32 spccr; /* SPDIF Clock Control Register */ |
| 176 | u32 cccr; /* CFM Clock Control Register */ |
| 177 | u32 dccr; /* DIU Clock Control Register */ |
| 178 | u32 msccr[4]; /* MSCAN1-4 Clock Control Registers */ |
| 179 | u8 res1[0x98]; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 180 | } clk512x_t; |
| 181 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 182 | /* SPMR - System PLL Mode Register */ |
| 183 | #define SPMR_SPMF 0x0F000000 |
| 184 | #define SPMR_SPMF_SHIFT 24 |
| 185 | #define SPMR_CPMF 0x000F0000 |
| 186 | #define SPMR_CPMF_SHIFT 16 |
| 187 | |
| 188 | /* System Clock Control Register 1 commands */ |
| 189 | #define CLOCK_SCCR1_CFG_EN 0x80000000 |
| 190 | #define CLOCK_SCCR1_LPC_EN 0x40000000 |
| 191 | #define CLOCK_SCCR1_NFC_EN 0x20000000 |
| 192 | #define CLOCK_SCCR1_PATA_EN 0x10000000 |
| 193 | #define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) |
| 194 | #define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 |
| 195 | #define CLOCK_SCCR1_SATA_EN 0x00004000 |
| 196 | #define CLOCK_SCCR1_FEC_EN 0x00002000 |
| 197 | #define CLOCK_SCCR1_TPR_EN 0x00001000 |
| 198 | #define CLOCK_SCCR1_PCI_EN 0x00000800 |
| 199 | #define CLOCK_SCCR1_DDR_EN 0x00000400 |
| 200 | |
| 201 | /* System Clock Control Register 2 commands */ |
| 202 | #define CLOCK_SCCR2_DIU_EN 0x80000000 |
| 203 | #define CLOCK_SCCR2_AXE_EN 0x40000000 |
| 204 | #define CLOCK_SCCR2_MEM_EN 0x20000000 |
Martha Stan | 3054eb4 | 2009-10-07 04:38:46 -0400 | [diff] [blame] | 205 | #define CLOCK_SCCR2_USB1_EN 0x10000000 |
| 206 | #define CLOCK_SCCR2_USB2_EN 0x08000000 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 207 | #define CLOCK_SCCR2_I2C_EN 0x04000000 |
| 208 | #define CLOCK_SCCR2_BDLC_EN 0x02000000 |
| 209 | #define CLOCK_SCCR2_SDHC_EN 0x01000000 |
| 210 | #define CLOCK_SCCR2_SPDIF_EN 0x00800000 |
| 211 | #define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 |
| 212 | #define CLOCK_SCCR2_MBX_EN 0x00200000 |
| 213 | #define CLOCK_SCCR2_MBX_3D_EN 0x00100000 |
| 214 | #define CLOCK_SCCR2_IIM_EN 0x00080000 |
| 215 | |
| 216 | /* SCFR1 System Clock Frequency Register 1 */ |
Anatolij Gustschin | a4911f5 | 2013-02-08 00:03:47 +0000 | [diff] [blame] | 217 | #ifndef SCFR1_IPS_DIV |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 218 | #define SCFR1_IPS_DIV 0x3 |
Anatolij Gustschin | a4911f5 | 2013-02-08 00:03:47 +0000 | [diff] [blame] | 219 | #endif |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 220 | #define SCFR1_IPS_DIV_MASK 0x03800000 |
| 221 | #define SCFR1_IPS_DIV_SHIFT 23 |
| 222 | |
| 223 | #define SCFR1_PCI_DIV 0x6 |
| 224 | #define SCFR1_PCI_DIV_MASK 0x00700000 |
| 225 | #define SCFR1_PCI_DIV_SHIFT 20 |
| 226 | |
Stefan Roese | 5538b5f | 2009-06-09 11:50:05 +0200 | [diff] [blame] | 227 | #define SCFR1_LPC_DIV_MASK 0x00003800 |
| 228 | #define SCFR1_LPC_DIV_SHIFT 11 |
| 229 | |
Anatolij Gustschin | db20e91 | 2013-02-08 00:03:46 +0000 | [diff] [blame] | 230 | #define SCFR1_NFC_DIV_MASK 0x00000700 |
| 231 | #define SCFR1_NFC_DIV_SHIFT 8 |
| 232 | |
| 233 | #define SCFR1_DIU_DIV_MASK 0x000000FF |
| 234 | #define SCFR1_DIU_DIV_SHIFT 0 |
| 235 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 236 | /* SCFR2 System Clock Frequency Register 2 */ |
| 237 | #define SCFR2_SYS_DIV 0xFC000000 |
| 238 | #define SCFR2_SYS_DIV_SHIFT 26 |
| 239 | |
| 240 | /* SPCR - System Priority Configuration Register */ |
| 241 | #define SPCR_TBEN 0x00400000 /* E300 core time base unit enable */ |
| 242 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 243 | /* |
| 244 | * Power Management Control Module |
| 245 | */ |
| 246 | typedef struct pmc512x { |
| 247 | u8 fixme[0x100]; |
| 248 | } pmc512x_t; |
| 249 | |
| 250 | /* |
| 251 | * General purpose I/O module |
| 252 | */ |
| 253 | typedef struct gpio512x { |
Wolfgang Denk | fd3166d | 2009-05-16 10:47:42 +0200 | [diff] [blame] | 254 | u32 gpdir; |
| 255 | u32 gpodr; |
| 256 | u32 gpdat; |
| 257 | u32 gpier; |
| 258 | u32 gpimr; |
| 259 | u32 gpicr1; |
| 260 | u32 gpicr2; |
| 261 | u8 res0[0xE4]; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 262 | } gpio512x_t; |
| 263 | |
| 264 | /* |
| 265 | * DDR Memory Controller Memory Map |
| 266 | */ |
| 267 | typedef struct ddr512x { |
| 268 | u32 ddr_sys_config; /* System Configuration Register */ |
| 269 | u32 ddr_time_config0; /* Timing Configuration Register */ |
| 270 | u32 ddr_time_config1; /* Timing Configuration Register */ |
| 271 | u32 ddr_time_config2; /* Timing Configuration Register */ |
| 272 | u32 ddr_command; /* Command Register */ |
| 273 | u32 ddr_compact_command; /* Compact Command Register */ |
| 274 | u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */ |
| 275 | u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */ |
| 276 | u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */ |
| 277 | u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */ |
| 278 | u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */ |
| 279 | u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ |
| 280 | u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ |
| 281 | u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame^] | 282 | u32 dqs_config_offset_count; /* DQS Config Offset Count */ |
| 283 | u32 dqs_config_offset_time; /* DQS Config Offset Time */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 284 | u32 DQS_delay_status; /* DQS Delay Status */ |
| 285 | u32 res0[0xF]; |
| 286 | u32 prioman_config1; /* Priority Manager Configuration */ |
| 287 | u32 prioman_config2; /* Priority Manager Configuration */ |
| 288 | u32 hiprio_config; /* High Priority Configuration */ |
| 289 | u32 lut_table0_main_upper; /* LUT0 Main Upper */ |
| 290 | u32 lut_table1_main_upper; /* LUT1 Main Upper */ |
| 291 | u32 lut_table2_main_upper; /* LUT2 Main Upper */ |
| 292 | u32 lut_table3_main_upper; /* LUT3 Main Upper */ |
| 293 | u32 lut_table4_main_upper; /* LUT4 Main Upper */ |
| 294 | u32 lut_table0_main_lower; /* LUT0 Main Lower */ |
| 295 | u32 lut_table1_main_lower; /* LUT1 Main Lower */ |
| 296 | u32 lut_table2_main_lower; /* LUT2 Main Lower */ |
| 297 | u32 lut_table3_main_lower; /* LUT3 Main Lower */ |
| 298 | u32 lut_table4_main_lower; /* LUT4 Main Lower */ |
| 299 | u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */ |
| 300 | u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */ |
| 301 | u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */ |
| 302 | u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */ |
| 303 | u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */ |
| 304 | u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */ |
| 305 | u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */ |
| 306 | u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */ |
| 307 | u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */ |
| 308 | u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */ |
| 309 | u32 performance_monitor_config; |
| 310 | u32 event_time_counter; |
| 311 | u32 event_time_preset; |
| 312 | u32 performance_monitor1_address_low; |
| 313 | u32 performance_monitor2_address_low; |
| 314 | u32 performance_monitor1_address_hi; |
| 315 | u32 performance_monitor2_address_hi; |
| 316 | u32 res1[2]; |
| 317 | u32 performance_monitor1_read_counter; |
| 318 | u32 performance_monitor2_read_counter; |
| 319 | u32 performance_monitor1_write_counter; |
| 320 | u32 performance_monitor2_write_counter; |
| 321 | u32 granted_ack_counter0; |
| 322 | u32 granted_ack_counter1; |
| 323 | u32 granted_ack_counter2; |
| 324 | u32 granted_ack_counter3; |
| 325 | u32 granted_ack_counter4; |
| 326 | u32 cumulative_wait_counter0; |
| 327 | u32 cumulative_wait_counter1; |
| 328 | u32 cumulative_wait_counter2; |
| 329 | u32 cumulative_wait_counter3; |
| 330 | u32 cumulative_wait_counter4; |
| 331 | u32 summed_priority_counter0; |
| 332 | u32 summed_priority_counter1; |
| 333 | u32 summed_priority_counter2; |
| 334 | u32 summed_priority_counter3; |
| 335 | u32 summed_priority_counter4; |
| 336 | u32 res2[0x3AD]; |
| 337 | } ddr512x_t; |
| 338 | |
Martha M Stan | c12ecae | 2009-09-21 14:07:14 -0400 | [diff] [blame] | 339 | /* MDDRC SYS CFG and Timing CFG0 Registers */ |
| 340 | #define MDDRC_SYS_CFG_EN 0xF0000000 |
Anatolij Gustschin | 32a7cb3 | 2013-02-08 00:03:49 +0000 | [diff] [blame] | 341 | #define MDDRC_SYS_CFG_CKE_MASK 0x40000000 |
Martha M Stan | c12ecae | 2009-09-21 14:07:14 -0400 | [diff] [blame] | 342 | #define MDDRC_SYS_CFG_CMD_MASK 0x10000000 |
| 343 | #define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 344 | |
| 345 | /* |
Wolfgang Denk | ce33a01 | 2009-10-04 22:56:08 +0200 | [diff] [blame] | 346 | * DDR Memory Controller Configuration settings |
| 347 | */ |
| 348 | typedef struct ddr512x_config { |
| 349 | u32 ddr_sys_config; /* System Configuration Register */ |
| 350 | u32 ddr_time_config0; /* Timing Configuration Register */ |
| 351 | u32 ddr_time_config1; /* Timing Configuration Register */ |
| 352 | u32 ddr_time_config2; /* Timing Configuration Register */ |
| 353 | } ddr512x_config_t; |
| 354 | |
Anatolij Gustschin | 81cad14 | 2010-04-24 19:27:09 +0200 | [diff] [blame] | 355 | typedef struct sdram_conf_s { |
| 356 | unsigned long size; |
| 357 | ddr512x_config_t cfg; |
| 358 | } sdram_conf_t; |
| 359 | |
Wolfgang Denk | ce33a01 | 2009-10-04 22:56:08 +0200 | [diff] [blame] | 360 | /* |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 361 | * DMA/Messaging Unit |
| 362 | */ |
| 363 | typedef struct dma512x { |
| 364 | u8 fixme[0x1800]; |
| 365 | } dma512x_t; |
| 366 | |
| 367 | /* |
| 368 | * PCI Software Configuration Registers |
| 369 | */ |
| 370 | typedef struct pciconf512x { |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 371 | u32 config_address; |
| 372 | u32 config_data; |
| 373 | u32 int_ack; |
| 374 | u8 res[116]; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 375 | } pciconf512x_t; |
| 376 | |
| 377 | /* |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 378 | * PCI Outbound Translation Register |
| 379 | */ |
| 380 | typedef struct pci_outbound_window { |
| 381 | u32 potar; |
| 382 | u8 res0[4]; |
| 383 | u32 pobar; |
| 384 | u8 res1[4]; |
| 385 | u32 pocmr; |
| 386 | u8 res2[4]; |
| 387 | } pot512x_t; |
| 388 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 389 | /* POTAR - PCI Outbound Translation Address Register */ |
| 390 | #define POTAR_TA_MASK 0x000fffff |
| 391 | |
| 392 | /* POBAR - PCI Outbound Base Address Register */ |
| 393 | #define POBAR_BA_MASK 0x000fffff |
| 394 | |
| 395 | /* POCMR - PCI Outbound Comparision Mask Register */ |
| 396 | #define POCMR_EN 0x80000000 |
| 397 | #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ |
| 398 | #define POCMR_PRE 0x20000000 /* prefetch enable */ |
| 399 | #define POCMR_SBS 0x00100000 /* special byte swap enable */ |
| 400 | #define POCMR_CM_MASK 0x000fffff |
| 401 | #define POCMR_CM_4G 0x00000000 |
| 402 | #define POCMR_CM_2G 0x00080000 |
| 403 | #define POCMR_CM_1G 0x000C0000 |
| 404 | #define POCMR_CM_512M 0x000E0000 |
| 405 | #define POCMR_CM_256M 0x000F0000 |
| 406 | #define POCMR_CM_128M 0x000F8000 |
| 407 | #define POCMR_CM_64M 0x000FC000 |
| 408 | #define POCMR_CM_32M 0x000FE000 |
| 409 | #define POCMR_CM_16M 0x000FF000 |
| 410 | #define POCMR_CM_8M 0x000FF800 |
| 411 | #define POCMR_CM_4M 0x000FFC00 |
| 412 | #define POCMR_CM_2M 0x000FFE00 |
| 413 | #define POCMR_CM_1M 0x000FFF00 |
| 414 | #define POCMR_CM_512K 0x000FFF80 |
| 415 | #define POCMR_CM_256K 0x000FFFC0 |
| 416 | #define POCMR_CM_128K 0x000FFFE0 |
| 417 | #define POCMR_CM_64K 0x000FFFF0 |
| 418 | #define POCMR_CM_32K 0x000FFFF8 |
| 419 | #define POCMR_CM_16K 0x000FFFFC |
| 420 | #define POCMR_CM_8K 0x000FFFFE |
| 421 | #define POCMR_CM_4K 0x000FFFFF |
| 422 | |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 423 | /* |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 424 | * Sequencer |
| 425 | */ |
| 426 | typedef struct ios512x { |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 427 | pot512x_t pot[6]; |
| 428 | u8 res0[0x60]; |
| 429 | u32 pmcr; |
| 430 | u8 res1[4]; |
| 431 | u32 dtcr; |
| 432 | u8 res2[4]; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 433 | } ios512x_t; |
| 434 | |
| 435 | /* |
| 436 | * PCI Controller |
| 437 | */ |
| 438 | typedef struct pcictrl512x { |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 439 | u32 esr; |
| 440 | u32 ecdr; |
| 441 | u32 eer; |
| 442 | u32 eatcr; |
| 443 | u32 eacr; |
| 444 | u32 eeacr; |
| 445 | u32 edlcr; |
| 446 | u32 edhcr; |
| 447 | u32 gcr; |
| 448 | u32 ecr; |
| 449 | u32 gsr; |
| 450 | u8 res0[12]; |
| 451 | u32 pitar2; |
| 452 | u8 res1[4]; |
| 453 | u32 pibar2; |
| 454 | u32 piebar2; |
| 455 | u32 piwar2; |
| 456 | u8 res2[4]; |
| 457 | u32 pitar1; |
| 458 | u8 res3[4]; |
| 459 | u32 pibar1; |
| 460 | u32 piebar1; |
| 461 | u32 piwar1; |
| 462 | u8 res4[4]; |
| 463 | u32 pitar0; |
| 464 | u8 res5[4]; |
| 465 | u32 pibar0; |
| 466 | u8 res6[4]; |
| 467 | u32 piwar0; |
| 468 | u8 res7[132]; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 469 | } pcictrl512x_t; |
| 470 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 471 | |
| 472 | /* PITAR - PCI Inbound Translation Address Register |
| 473 | */ |
| 474 | #define PITAR_TA_MASK 0x000fffff |
| 475 | |
| 476 | /* PIBAR - PCI Inbound Base/Extended Address Register |
| 477 | */ |
| 478 | #define PIBAR_MASK 0xffffffff |
| 479 | #define PIEBAR_EBA_MASK 0x000fffff |
| 480 | |
| 481 | /* PIWAR - PCI Inbound Windows Attributes Register |
| 482 | */ |
| 483 | #define PIWAR_EN 0x80000000 |
| 484 | #define PIWAR_SBS 0x40000000 |
| 485 | #define PIWAR_PF 0x20000000 |
| 486 | #define PIWAR_RTT_MASK 0x000f0000 |
| 487 | #define PIWAR_RTT_NO_SNOOP 0x00040000 |
| 488 | #define PIWAR_RTT_SNOOP 0x00050000 |
| 489 | #define PIWAR_WTT_MASK 0x0000f000 |
| 490 | #define PIWAR_WTT_NO_SNOOP 0x00004000 |
| 491 | #define PIWAR_WTT_SNOOP 0x00005000 |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 492 | |
| 493 | /* |
| 494 | * MSCAN |
| 495 | */ |
| 496 | typedef struct mscan512x { |
| 497 | u8 fixme[0x100]; |
| 498 | } mscan512x_t; |
| 499 | |
| 500 | /* |
| 501 | * BDLC |
| 502 | */ |
| 503 | typedef struct bdlc512x { |
| 504 | u8 fixme[0x100]; |
| 505 | } bdlc512x_t; |
| 506 | |
| 507 | /* |
| 508 | * SDHC |
| 509 | */ |
| 510 | typedef struct sdhc512x { |
| 511 | u8 fixme[0x100]; |
| 512 | } sdhc512x_t; |
| 513 | |
| 514 | /* |
| 515 | * SPDIF |
| 516 | */ |
| 517 | typedef struct spdif512x { |
| 518 | u8 fixme[0x100]; |
| 519 | } spdif512x_t; |
| 520 | |
| 521 | /* |
| 522 | * I2C |
| 523 | */ |
| 524 | typedef struct i2c512x_dev { |
| 525 | volatile u32 madr; /* I2Cn + 0x00 */ |
| 526 | volatile u32 mfdr; /* I2Cn + 0x04 */ |
| 527 | volatile u32 mcr; /* I2Cn + 0x08 */ |
| 528 | volatile u32 msr; /* I2Cn + 0x0C */ |
| 529 | volatile u32 mdr; /* I2Cn + 0x10 */ |
| 530 | u8 res0[0x0C]; |
| 531 | } i2c512x_dev_t; |
| 532 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 533 | /* Number of I2C buses */ |
| 534 | #define I2C_BUS_CNT 3 |
| 535 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 536 | typedef struct i2c512x { |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 537 | i2c512x_dev_t dev[I2C_BUS_CNT]; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 538 | volatile u32 icr; |
| 539 | volatile u32 mifr; |
| 540 | u8 res0[0x98]; |
| 541 | } i2c512x_t; |
| 542 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 543 | /* I2Cn control register bits */ |
| 544 | #define I2C_EN 0x80 |
| 545 | #define I2C_IEN 0x40 |
| 546 | #define I2C_STA 0x20 |
| 547 | #define I2C_TX 0x10 |
| 548 | #define I2C_TXAK 0x08 |
| 549 | #define I2C_RSTA 0x04 |
| 550 | #define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) |
| 551 | |
| 552 | /* I2Cn status register bits */ |
| 553 | #define I2C_CF 0x80 |
| 554 | #define I2C_AAS 0x40 |
| 555 | #define I2C_BB 0x20 |
| 556 | #define I2C_AL 0x10 |
| 557 | #define I2C_SRW 0x04 |
| 558 | #define I2C_IF 0x02 |
| 559 | #define I2C_RXAK 0x01 |
| 560 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 561 | /* |
| 562 | * AXE |
| 563 | */ |
| 564 | typedef struct axe512x { |
| 565 | u8 fixme[0x100]; |
| 566 | } axe512x_t; |
| 567 | |
| 568 | /* |
| 569 | * DIU |
| 570 | */ |
| 571 | typedef struct diu512x { |
| 572 | u8 fixme[0x100]; |
| 573 | } diu512x_t; |
| 574 | |
| 575 | /* |
| 576 | * CFM |
| 577 | */ |
| 578 | typedef struct cfm512x { |
| 579 | u8 fixme[0x100]; |
| 580 | } cfm512x_t; |
| 581 | |
| 582 | /* |
| 583 | * FEC |
| 584 | */ |
| 585 | typedef struct fec512x { |
Wolfgang Denk | fd3166d | 2009-05-16 10:47:42 +0200 | [diff] [blame] | 586 | u32 fec_id; /* FEC_ID register */ |
| 587 | u32 ievent; /* Interrupt event register */ |
| 588 | u32 imask; /* Interrupt mask register */ |
| 589 | u32 reserved_01; |
| 590 | u32 r_des_active; /* Receive ring updated flag */ |
| 591 | u32 x_des_active; /* Transmit ring updated flag */ |
| 592 | u32 reserved_02[3]; |
| 593 | u32 ecntrl; /* Ethernet control register */ |
| 594 | u32 reserved_03[6]; |
| 595 | u32 mii_data; /* MII data register */ |
| 596 | u32 mii_speed; /* MII speed register */ |
| 597 | u32 reserved_04[7]; |
| 598 | u32 mib_control; /* MIB control/status register */ |
| 599 | u32 reserved_05[7]; |
| 600 | u32 r_cntrl; /* Receive control register */ |
| 601 | u32 r_hash; /* Receive hash */ |
| 602 | u32 reserved_06[14]; |
| 603 | u32 x_cntrl; /* Transmit control register */ |
| 604 | u32 reserved_07[7]; |
| 605 | u32 paddr1; /* Physical address low */ |
| 606 | u32 paddr2; /* Physical address high + type field */ |
| 607 | u32 op_pause; /* Opcode + pause duration */ |
| 608 | u32 reserved_08[10]; |
| 609 | u32 iaddr1; /* Upper 32 bits of individual hash table */ |
| 610 | u32 iaddr2; /* Lower 32 bits of individual hash table */ |
| 611 | u32 gaddr1; /* Upper 32 bits of group hash table */ |
| 612 | u32 gaddr2; /* Lower 32 bits of group hash table */ |
| 613 | u32 reserved_09[7]; |
| 614 | u32 x_wmrk; /* Transmit FIFO watermark */ |
| 615 | u32 reserved_10; |
| 616 | u32 r_bound; /* End of RAM */ |
| 617 | u32 r_fstart; /* Receive FIFO start address */ |
| 618 | u32 reserved_11[11]; |
| 619 | u32 r_des_start; /* Beginning of receive descriptor ring */ |
| 620 | u32 x_des_start; /* Pointer to beginning of transmit descriptor ring */ |
| 621 | u32 r_buff_size; /* Receive buffer size */ |
| 622 | u32 reserved_12[26]; |
| 623 | u32 dma_control; /* DMA control for IP bus, AMBA IF + DMA revision */ |
| 624 | u32 reserved_13[2]; |
| 625 | |
| 626 | u32 mib[128]; /* MIB Block Counters */ |
| 627 | |
| 628 | u32 fifo[256]; /* used by FEC, can only be accessed by DMA */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 629 | } fec512x_t; |
| 630 | |
| 631 | /* |
| 632 | * ULPI |
| 633 | */ |
| 634 | typedef struct ulpi512x { |
| 635 | u8 fixme[0x600]; |
| 636 | } ulpi512x_t; |
| 637 | |
| 638 | /* |
| 639 | * UTMI |
| 640 | */ |
| 641 | typedef struct utmi512x { |
| 642 | u8 fixme[0x3000]; |
| 643 | } utmi512x_t; |
| 644 | |
| 645 | /* |
| 646 | * PCI DMA |
| 647 | */ |
| 648 | typedef struct pcidma512x { |
| 649 | u8 fixme[0x300]; |
| 650 | } pcidma512x_t; |
| 651 | |
| 652 | /* |
| 653 | * IO Control |
| 654 | */ |
| 655 | typedef struct ioctrl512x { |
Wolfgang Denk | fd3166d | 2009-05-16 10:47:42 +0200 | [diff] [blame] | 656 | u32 io_control_mem; /* MEM pad ctrl reg */ |
| 657 | u32 io_control_gp; /* GP pad ctrl reg */ |
| 658 | u32 io_control_lpc_clk; /* LPC_CLK pad ctrl reg */ |
| 659 | u32 io_control_lpc_oe; /* LPC_OE pad ctrl reg */ |
| 660 | u32 io_control_lpc_rw; /* LPC_R/W pad ctrl reg */ |
| 661 | u32 io_control_lpc_ack; /* LPC_ACK pad ctrl reg */ |
| 662 | u32 io_control_lpc_cs0; /* LPC_CS0 pad ctrl reg */ |
| 663 | u32 io_control_nfc_ce0; /* NFC_CE0 pad ctrl reg */ |
| 664 | u32 io_control_lpc_cs1; /* LPC_CS1 pad ctrl reg */ |
| 665 | u32 io_control_lpc_cs2; /* LPC_CS2 pad ctrl reg */ |
| 666 | u32 io_control_lpc_ax03; /* LPC_AX03 pad ctrl reg */ |
| 667 | u32 io_control_emb_ax02; /* EMB_AX02 pad ctrl reg */ |
| 668 | u32 io_control_emb_ax01; /* EMB_AX01 pad ctrl reg */ |
| 669 | u32 io_control_emb_ax00; /* EMB_AX00 pad ctrl reg */ |
| 670 | u32 io_control_emb_ad31; /* EMB_AD31 pad ctrl reg */ |
| 671 | u32 io_control_emb_ad30; /* EMB_AD30 pad ctrl reg */ |
| 672 | u32 io_control_emb_ad29; /* EMB_AD29 pad ctrl reg */ |
| 673 | u32 io_control_emb_ad28; /* EMB_AD28 pad ctrl reg */ |
| 674 | u32 io_control_emb_ad27; /* EMB_AD27 pad ctrl reg */ |
| 675 | u32 io_control_emb_ad26; /* EMB_AD26 pad ctrl reg */ |
| 676 | u32 io_control_emb_ad25; /* EMB_AD25 pad ctrl reg */ |
| 677 | u32 io_control_emb_ad24; /* EMB_AD24 pad ctrl reg */ |
| 678 | u32 io_control_emb_ad23; /* EMB_AD23 pad ctrl reg */ |
| 679 | u32 io_control_emb_ad22; /* EMB_AD22 pad ctrl reg */ |
| 680 | u32 io_control_emb_ad21; /* EMB_AD21 pad ctrl reg */ |
| 681 | u32 io_control_emb_ad20; /* EMB_AD20 pad ctrl reg */ |
| 682 | u32 io_control_emb_ad19; /* EMB_AD19 pad ctrl reg */ |
| 683 | u32 io_control_emb_ad18; /* EMB_AD18 pad ctrl reg */ |
| 684 | u32 io_control_emb_ad17; /* EMB_AD17 pad ctrl reg */ |
| 685 | u32 io_control_emb_ad16; /* EMB_AD16 pad ctrl reg */ |
| 686 | u32 io_control_emb_ad15; /* EMB_AD15 pad ctrl reg */ |
| 687 | u32 io_control_emb_ad14; /* EMB_AD14 pad ctrl reg */ |
| 688 | u32 io_control_emb_ad13; /* EMB_AD13 pad ctrl reg */ |
| 689 | u32 io_control_emb_ad12; /* EMB_AD12 pad ctrl reg */ |
| 690 | u32 io_control_emb_ad11; /* EMB_AD11 pad ctrl reg */ |
| 691 | u32 io_control_emb_ad10; /* EMB_AD10 pad ctrl reg */ |
| 692 | u32 io_control_emb_ad09; /* EMB_AD09 pad ctrl reg */ |
| 693 | u32 io_control_emb_ad08; /* EMB_AD08 pad ctrl reg */ |
| 694 | u32 io_control_emb_ad07; /* EMB_AD07 pad ctrl reg */ |
| 695 | u32 io_control_emb_ad06; /* EMB_AD06 pad ctrl reg */ |
| 696 | u32 io_control_emb_ad05; /* EMB_AD05 pad ctrl reg */ |
| 697 | u32 io_control_emb_ad04; /* EMB_AD04 pad ctrl reg */ |
| 698 | u32 io_control_emb_ad03; /* EMB_AD03 pad ctrl reg */ |
| 699 | u32 io_control_emb_ad02; /* EMB_AD02 pad ctrl reg */ |
| 700 | u32 io_control_emb_ad01; /* EMB_AD01 pad ctrl reg */ |
| 701 | u32 io_control_emb_ad00; /* EMB_AD00 pad ctrl reg */ |
| 702 | u32 io_control_pata_ce1; /* PATA_CE1 pad ctrl reg */ |
| 703 | u32 io_control_pata_ce2; /* PATA_CE2 pad ctrl reg */ |
| 704 | u32 io_control_pata_isolate; /* PATA_ISOLATE pad ctrl reg */ |
| 705 | u32 io_control_pata_ior; /* PATA_IOR pad ctrl reg */ |
| 706 | u32 io_control_pata_iow; /* PATA_IOW pad ctrl reg */ |
| 707 | u32 io_control_pata_iochrdy; /* PATA_IOCHRDY pad ctrl reg */ |
| 708 | u32 io_control_pata_intrq; /* PATA_INTRQ pad ctrl reg */ |
| 709 | u32 io_control_pata_drq; /* PATA_DRQ pad ctrl reg */ |
| 710 | u32 io_control_pata_dack; /* PATA_DACK pad ctrl reg */ |
| 711 | u32 io_control_nfc_wp; /* NFC_WP pad ctrl reg */ |
| 712 | u32 io_control_nfc_rb; /* NFC_RB pad ctrl reg */ |
| 713 | u32 io_control_nfc_ale; /* NFC_ALE pad ctrl reg */ |
| 714 | u32 io_control_nfc_cle; /* NFC_CLE pad ctrl reg */ |
| 715 | u32 io_control_nfc_we; /* NFC_WE pad ctrl reg */ |
| 716 | u32 io_control_nfc_re; /* NFC_RE pad ctrl reg */ |
| 717 | u32 io_control_pci_ad31; /* PCI_AD31 pad ctrl reg */ |
| 718 | u32 io_control_pci_ad30; /* PCI_AD30 pad ctrl reg */ |
| 719 | u32 io_control_pci_ad29; /* PCI_AD29 pad ctrl reg */ |
| 720 | u32 io_control_pci_ad28; /* PCI_AD28 pad ctrl reg */ |
| 721 | u32 io_control_pci_ad27; /* PCI_AD27 pad ctrl reg */ |
| 722 | u32 io_control_pci_ad26; /* PCI_AD26 pad ctrl reg */ |
| 723 | u32 io_control_pci_ad25; /* PCI_AD25 pad ctrl reg */ |
| 724 | u32 io_control_pci_ad24; /* PCI_AD24 pad ctrl reg */ |
| 725 | u32 io_control_pci_ad23; /* PCI_AD23 pad ctrl reg */ |
| 726 | u32 io_control_pci_ad22; /* PCI_AD22 pad ctrl reg */ |
| 727 | u32 io_control_pci_ad21; /* PCI_AD21 pad ctrl reg */ |
| 728 | u32 io_control_pci_ad20; /* PCI_AD20 pad ctrl reg */ |
| 729 | u32 io_control_pci_ad19; /* PCI_AD19 pad ctrl reg */ |
| 730 | u32 io_control_pci_ad18; /* PCI_AD18 pad ctrl reg */ |
| 731 | u32 io_control_pci_ad17; /* PCI_AD17 pad ctrl reg */ |
| 732 | u32 io_control_pci_ad16; /* PCI_AD16 pad ctrl reg */ |
| 733 | u32 io_control_pci_ad15; /* PCI_AD15 pad ctrl reg */ |
| 734 | u32 io_control_pci_ad14; /* PCI_AD14 pad ctrl reg */ |
| 735 | u32 io_control_pci_ad13; /* PCI_AD13 pad ctrl reg */ |
| 736 | u32 io_control_pci_ad12; /* PCI_AD12 pad ctrl reg */ |
| 737 | u32 io_control_pci_ad11; /* PCI_AD11 pad ctrl reg */ |
| 738 | u32 io_control_pci_ad10; /* PCI_AD10 pad ctrl reg */ |
| 739 | u32 io_control_pci_ad09; /* PCI_AD09 pad ctrl reg */ |
| 740 | u32 io_control_pci_ad08; /* PCI_AD08 pad ctrl reg */ |
| 741 | u32 io_control_pci_ad07; /* PCI_AD07 pad ctrl reg */ |
| 742 | u32 io_control_pci_ad06; /* PCI_AD06 pad ctrl reg */ |
| 743 | u32 io_control_pci_ad05; /* PCI_AD05 pad ctrl reg */ |
| 744 | u32 io_control_pci_ad04; /* PCI_AD04 pad ctrl reg */ |
| 745 | u32 io_control_pci_ad03; /* PCI_AD03 pad ctrl reg */ |
| 746 | u32 io_control_pci_ad02; /* PCI_AD02 pad ctrl reg */ |
| 747 | u32 io_control_pci_ad01; /* PCI_AD01 pad ctrl reg */ |
| 748 | u32 io_control_pci_ad00; /* PCI_AD00 pad ctrl reg */ |
| 749 | u32 io_control_pci_cbe0; /* PCI_CBE0 pad ctrl reg */ |
| 750 | u32 io_control_pci_cbe1; /* PCI_CBE1 pad ctrl reg */ |
| 751 | u32 io_control_pci_cbe2; /* PCI_CBE2 pad ctrl reg */ |
| 752 | u32 io_control_pci_cbe3; /* PCI_CBE3 pad ctrl reg */ |
| 753 | u32 io_control_pci_grant2; /* PCI_GRANT2 pad ctrl reg */ |
| 754 | u32 io_control_pci_req2; /* PCI_REQ2 pad ctrl reg */ |
| 755 | u32 io_control_pci_grant1; /* PCI_GRANT1 pad ctrl reg */ |
| 756 | u32 io_control_pci_req1; /* PCI_REQ1 pad ctrl reg */ |
| 757 | u32 io_control_pci_grant0; /* PCI_GRANT0 pad ctrl reg */ |
| 758 | u32 io_control_pci_req0; /* PCI_REQ0 pad ctrl reg */ |
| 759 | u32 io_control_pci_inta; /* PCI_INTA pad ctrl reg */ |
| 760 | u32 io_control_pci_clk; /* PCI_CLK pad ctrl reg */ |
| 761 | u32 io_control_pci_rst; /* PCI_RST- pad ctrl reg */ |
| 762 | u32 io_control_pci_frame; /* PCI_FRAME pad ctrl reg */ |
| 763 | u32 io_control_pci_idsel; /* PCI_IDSEL pad ctrl reg */ |
| 764 | u32 io_control_pci_devsel; /* PCI_DEVSEL pad ctrl reg */ |
| 765 | u32 io_control_pci_irdy; /* PCI_IRDY pad ctrl reg */ |
| 766 | u32 io_control_pci_trdy; /* PCI_TRDY pad ctrl reg */ |
| 767 | u32 io_control_pci_stop; /* PCI_STOP pad ctrl reg */ |
| 768 | u32 io_control_pci_par; /* PCI_PAR pad ctrl reg */ |
| 769 | u32 io_control_pci_perr; /* PCI_PERR pad ctrl reg */ |
| 770 | u32 io_control_pci_serr; /* PCI_SERR pad ctrl reg */ |
| 771 | u32 io_control_spdif_txclk; /* SPDIF_TXCLK pad ctrl reg */ |
| 772 | u32 io_control_spdif_tx; /* SPDIF_TX pad ctrl reg */ |
| 773 | u32 io_control_spdif_rx; /* SPDIF_RX pad ctrl reg */ |
| 774 | u32 io_control_i2c0_scl; /* I2C0_SCL pad ctrl reg */ |
| 775 | u32 io_control_i2c0_sda; /* I2C0_SDA pad ctrl reg */ |
| 776 | u32 io_control_i2c1_scl; /* I2C1_SCL pad ctrl reg */ |
| 777 | u32 io_control_i2c1_sda; /* I2C1_SDA pad ctrl reg */ |
| 778 | u32 io_control_i2c2_scl; /* I2C2_SCL pad ctrl reg */ |
| 779 | u32 io_control_i2c2_sda; /* I2C2_SDA pad ctrl reg */ |
| 780 | u32 io_control_irq0; /* IRQ0 pad ctrl reg */ |
| 781 | u32 io_control_irq1; /* IRQ1 pad ctrl reg */ |
| 782 | u32 io_control_can1_tx; /* CAN1_TX pad ctrl reg */ |
| 783 | u32 io_control_can2_tx; /* CAN2_TX pad ctrl reg */ |
| 784 | u32 io_control_j1850_tx; /* J1850_TX pad ctrl reg */ |
| 785 | u32 io_control_j1850_rx; /* J1850_RX pad ctrl reg */ |
| 786 | u32 io_control_psc_mclk_in; /* PSC_MCLK_IN pad ctrl reg */ |
| 787 | u32 io_control_psc0_0; /* PSC0_0 pad ctrl reg */ |
| 788 | u32 io_control_psc0_1; /* PSC0_1 pad ctrl reg */ |
| 789 | u32 io_control_psc0_2; /* PSC0_2 pad ctrl reg */ |
| 790 | u32 io_control_psc0_3; /* PSC0_3 pad ctrl reg */ |
| 791 | u32 io_control_psc0_4; /* PSC0_4 pad ctrl reg */ |
| 792 | u32 io_control_psc1_0; /* PSC1_0 pad ctrl reg */ |
| 793 | u32 io_control_psc1_1; /* PSC1_1 pad ctrl reg */ |
| 794 | u32 io_control_psc1_2; /* PSC1_2 pad ctrl reg */ |
| 795 | u32 io_control_psc1_3; /* PSC1_3 pad ctrl reg */ |
| 796 | u32 io_control_psc1_4; /* PSC1_4 pad ctrl reg */ |
| 797 | u32 io_control_psc2_0; /* PSC2_0 pad ctrl reg */ |
| 798 | u32 io_control_psc2_1; /* PSC2_1 pad ctrl reg */ |
| 799 | u32 io_control_psc2_2; /* PSC2_2 pad ctrl reg */ |
| 800 | u32 io_control_psc2_3; /* PSC2_3 pad ctrl reg */ |
| 801 | u32 io_control_psc2_4; /* PSC2_4 pad ctrl reg */ |
| 802 | u32 io_control_psc3_0; /* PSC3_0 pad ctrl reg */ |
| 803 | u32 io_control_psc3_1; /* PSC3_1 pad ctrl reg */ |
| 804 | u32 io_control_psc3_2; /* PSC3_2 pad ctrl reg */ |
| 805 | u32 io_control_psc3_3; /* PSC3_3 pad ctrl reg */ |
| 806 | u32 io_control_psc3_4; /* PSC3_4 pad ctrl reg */ |
| 807 | u32 io_control_psc4_0; /* PSC4_0 pad ctrl reg */ |
| 808 | u32 io_control_psc4_1; /* PSC4_1 pad ctrl reg */ |
| 809 | u32 io_control_psc4_2; /* PSC4_2 pad ctrl reg */ |
| 810 | u32 io_control_psc4_3; /* PSC4_3 pad ctrl reg */ |
| 811 | u32 io_control_psc4_4; /* PSC4_4 pad ctrl reg */ |
| 812 | u32 io_control_psc5_0; /* PSC5_0 pad ctrl reg */ |
| 813 | u32 io_control_psc5_1; /* PSC5_1 pad ctrl reg */ |
| 814 | u32 io_control_psc5_2; /* PSC5_2 pad ctrl reg */ |
| 815 | u32 io_control_psc5_3; /* PSC5_3 pad ctrl reg */ |
| 816 | u32 io_control_psc5_4; /* PSC5_4 pad ctrl reg */ |
| 817 | u32 io_control_psc6_0; /* PSC6_0 pad ctrl reg */ |
| 818 | u32 io_control_psc6_1; /* PSC6_1 pad ctrl reg */ |
| 819 | u32 io_control_psc6_2; /* PSC6_2 pad ctrl reg */ |
| 820 | u32 io_control_psc6_3; /* PSC6_3 pad ctrl reg */ |
| 821 | u32 io_control_psc6_4; /* PSC6_4 pad ctrl reg */ |
| 822 | u32 io_control_psc7_0; /* PSC7_0 pad ctrl reg */ |
| 823 | u32 io_control_psc7_1; /* PSC7_1 pad ctrl reg */ |
| 824 | u32 io_control_psc7_2; /* PSC7_2 pad ctrl reg */ |
| 825 | u32 io_control_psc7_3; /* PSC7_3 pad ctrl reg */ |
| 826 | u32 io_control_psc7_4; /* PSC7_4 pad ctrl reg */ |
| 827 | u32 io_control_psc8_0; /* PSC8_0 pad ctrl reg */ |
| 828 | u32 io_control_psc8_1; /* PSC8_1 pad ctrl reg */ |
| 829 | u32 io_control_psc8_2; /* PSC8_2 pad ctrl reg */ |
| 830 | u32 io_control_psc8_3; /* PSC8_3 pad ctrl reg */ |
| 831 | u32 io_control_psc8_4; /* PSC8_4 pad ctrl reg */ |
| 832 | u32 io_control_psc9_0; /* PSC9_0 pad ctrl reg */ |
| 833 | u32 io_control_psc9_1; /* PSC9_1 pad ctrl reg */ |
| 834 | u32 io_control_psc9_2; /* PSC9_2 pad ctrl reg */ |
| 835 | u32 io_control_psc9_3; /* PSC9_3 pad ctrl reg */ |
| 836 | u32 io_control_psc9_4; /* PSC9_4 pad ctrl reg */ |
| 837 | u32 io_control_psc10_0; /* PSC10_0 pad ctrl reg */ |
| 838 | u32 io_control_psc10_1; /* PSC10_1 pad ctrl reg */ |
| 839 | u32 io_control_psc10_2; /* PSC10_2 pad ctrl reg */ |
| 840 | u32 io_control_psc10_3; /* PSC10_3 pad ctrl reg */ |
| 841 | u32 io_control_psc10_4; /* PSC10_4 pad ctrl reg */ |
| 842 | u32 io_control_psc11_0; /* PSC11_0 pad ctrl reg */ |
| 843 | u32 io_control_psc11_1; /* PSC11_1 pad ctrl reg */ |
| 844 | u32 io_control_psc11_2; /* PSC11_2 pad ctrl reg */ |
| 845 | u32 io_control_psc11_3; /* PSC11_3 pad ctrl reg */ |
| 846 | u32 io_control_psc11_4; /* PSC11_4 pad ctrl reg */ |
| 847 | u32 io_control_ckstp_out; /* CKSTP_OUT pad ctrl reg */ |
| 848 | u32 io_control_usb_phy_drvvbus; /* USB2_DRVVBUS pad ctrl reg */ |
| 849 | u8 reserved[0x0cfc]; /* fill to 4096 bytes size */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 850 | } ioctrl512x_t; |
| 851 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 852 | /* IO pin fields */ |
| 853 | #define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ |
| 854 | #define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ |
| 855 | #define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ |
| 856 | #define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ |
| 857 | #define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ |
| 858 | #define IO_PIN_DS(v) ((v)) /* slew rate */ |
| 859 | |
| 860 | typedef struct iopin_t { |
| 861 | int p_offset; /* offset from IOCTL_MEM_OFFSET */ |
| 862 | int nr_pins; /* number of pins to set this way */ |
| 863 | int bit_or; /* or in the value instead of overwrite */ |
| 864 | u_long val; /* value to write or or */ |
| 865 | }iopin_t; |
| 866 | |
| 867 | void iopin_initialize(iopin_t *,int); |
| 868 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 869 | /* |
Anatolij Gustschin | d639890 | 2013-02-08 00:03:48 +0000 | [diff] [blame] | 870 | * support to adjust individual parts of the IO pin setup |
| 871 | */ |
| 872 | |
| 873 | #define IO_PIN_OVER_EACH (1 << 0) /* for compatibility */ |
| 874 | #define IO_PIN_OVER_FMUX (1 << 1) |
| 875 | #define IO_PIN_OVER_HOLD (1 << 2) |
| 876 | #define IO_PIN_OVER_PULL (1 << 3) |
| 877 | #define IO_PIN_OVER_STRIG (1 << 4) |
| 878 | #define IO_PIN_OVER_DRVSTR (1 << 5) |
| 879 | |
| 880 | void iopin_initialize_bits(iopin_t *, int); |
| 881 | |
| 882 | /* |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 883 | * IIM |
| 884 | */ |
| 885 | typedef struct iim512x { |
Martha Marx | 5d3e23f | 2009-01-26 10:45:07 -0700 | [diff] [blame] | 886 | u32 stat; /* IIM status register */ |
| 887 | u32 statm; /* IIM status IRQ mask */ |
| 888 | u32 err; /* IIM errors register */ |
| 889 | u32 emask; /* IIM error IRQ mask */ |
| 890 | u32 fctl; /* IIM fuse control register */ |
| 891 | u32 ua; /* IIM upper address register */ |
| 892 | u32 la; /* IIM lower address register */ |
| 893 | u32 sdat; /* IIM explicit sense data */ |
| 894 | u8 res0[0x08]; |
| 895 | u32 prg_p; /* IIM program protection register */ |
| 896 | u8 res1[0x10]; |
| 897 | u32 divide; /* IIM divide factor register */ |
| 898 | u8 res2[0x7c0]; |
| 899 | u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */ |
| 900 | u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */ |
| 901 | u8 res3[0x380]; |
| 902 | u32 fbac1; /* IIM fuse bank 1 protection */ |
| 903 | u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */ |
| 904 | u8 res4[0x380]; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 905 | } iim512x_t; |
| 906 | |
| 907 | /* |
| 908 | * LPC |
| 909 | */ |
| 910 | typedef struct lpc512x { |
| 911 | u32 cs_cfg[8]; /* Chip Select N Configuration Registers |
| 912 | No dedicated entry for CS Boot as == CS0 */ |
| 913 | u32 cs_cr; /* Chip Select Control Register */ |
| 914 | u32 cs_sr; /* Chip Select Status Register */ |
| 915 | u32 cs_bcr; /* Chip Select Burst Control Register */ |
| 916 | u32 cs_dccr; /* Chip Select Deadcycle Control Register */ |
| 917 | u32 cs_hccr; /* Chip Select Holdcycle Control Register */ |
Wolfgang Denk | fd3166d | 2009-05-16 10:47:42 +0200 | [diff] [blame] | 918 | u32 altr; /* Address Latch Timing Register */ |
| 919 | u8 res0[0xc8]; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 920 | u32 sclpc_psr; /* SCLPC Packet Size Register */ |
| 921 | u32 sclpc_sar; /* SCLPC Start Address Register */ |
| 922 | u32 sclpc_cr; /* SCLPC Control Register */ |
| 923 | u32 sclpc_er; /* SCLPC Enable Register */ |
| 924 | u32 sclpc_nar; /* SCLPC NextAddress Register */ |
| 925 | u32 sclpc_sr; /* SCLPC Status Register */ |
| 926 | u32 sclpc_bdr; /* SCLPC Bytes Done Register */ |
| 927 | u32 emb_scr; /* EMB Share Counter Register */ |
| 928 | u32 emb_pcr; /* EMB Pause Control Register */ |
| 929 | u8 res1[0x1c]; |
| 930 | u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */ |
| 931 | u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */ |
| 932 | u32 lpc_cr; /* LPC RX/TX FIFO Control Register */ |
| 933 | u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */ |
| 934 | u8 res2[0xb0]; |
| 935 | } lpc512x_t; |
| 936 | |
| 937 | /* |
| 938 | * PATA |
| 939 | */ |
| 940 | typedef struct pata512x { |
Ralph Kondziella | d074bfe | 2009-01-26 12:34:36 -0700 | [diff] [blame] | 941 | /* LOCAL Registers */ |
| 942 | u32 pata_time1; /* Time register 1: PIO and tx timing parameter */ |
| 943 | u32 pata_time2; /* Time register 2: PIO timing parameter */ |
| 944 | u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */ |
| 945 | u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */ |
| 946 | u32 pata_time5; /* Time register 5: UDMA timing parameter */ |
| 947 | u32 pata_time6; /* Time register 6: UDMA timing parameter */ |
| 948 | u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */ |
| 949 | u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */ |
| 950 | u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/ |
| 951 | u32 pata_ata_control; /* ATA Interface control register */ |
| 952 | u32 pata_irq_pending; /* Interrupt pending register (READONLY) */ |
| 953 | u32 pata_irq_enable; /* Interrupt enable register */ |
| 954 | u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/ |
| 955 | u32 pata_fifo_alarm; /* fifo alarm threshold */ |
| 956 | u32 res1[0x1A]; |
| 957 | /* DRIVE Registers */ |
| 958 | u32 pata_drive_data; /* drive data register*/ |
| 959 | u32 pata_drive_features;/* drive features register */ |
| 960 | u32 pata_drive_sectcnt; /* drive sector count register */ |
| 961 | u32 pata_drive_sectnum; /* drive sector number register */ |
| 962 | u32 pata_drive_cyllow; /* drive cylinder low register */ |
| 963 | u32 pata_drive_cylhigh; /* drive cylinder high register */ |
| 964 | u32 pata_drive_dev_head;/* drive device head register */ |
| 965 | u32 pata_drive_command; /* write = drive command, read = drive status reg */ |
| 966 | u32 res2[0x06]; |
| 967 | u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */ |
| 968 | u32 res3[0x09]; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 969 | } pata512x_t; |
| 970 | |
| 971 | /* |
| 972 | * PSC |
| 973 | */ |
| 974 | typedef struct psc512x { |
| 975 | volatile u8 mode; /* PSC + 0x00 */ |
| 976 | volatile u8 res0[3]; |
| 977 | union { /* PSC + 0x04 */ |
| 978 | volatile u16 status; |
| 979 | volatile u16 clock_select; |
| 980 | } sr_csr; |
| 981 | #define psc_status sr_csr.status |
| 982 | #define psc_clock_select sr_csr.clock_select |
| 983 | volatile u16 res1; |
| 984 | volatile u8 command; /* PSC + 0x08 */ |
| 985 | volatile u8 res2[3]; |
| 986 | union { /* PSC + 0x0c */ |
| 987 | volatile u8 buffer_8; |
| 988 | volatile u16 buffer_16; |
| 989 | volatile u32 buffer_32; |
| 990 | } buffer; |
| 991 | #define psc_buffer_8 buffer.buffer_8 |
| 992 | #define psc_buffer_16 buffer.buffer_16 |
| 993 | #define psc_buffer_32 buffer.buffer_32 |
| 994 | union { /* PSC + 0x10 */ |
| 995 | volatile u8 ipcr; |
| 996 | volatile u8 acr; |
| 997 | } ipcr_acr; |
| 998 | #define psc_ipcr ipcr_acr.ipcr |
| 999 | #define psc_acr ipcr_acr.acr |
| 1000 | volatile u8 res3[3]; |
| 1001 | union { /* PSC + 0x14 */ |
| 1002 | volatile u16 isr; |
| 1003 | volatile u16 imr; |
| 1004 | } isr_imr; |
| 1005 | #define psc_isr isr_imr.isr |
| 1006 | #define psc_imr isr_imr.imr |
| 1007 | volatile u16 res4; |
| 1008 | volatile u8 ctur; /* PSC + 0x18 */ |
| 1009 | volatile u8 res5[3]; |
| 1010 | volatile u8 ctlr; /* PSC + 0x1c */ |
| 1011 | volatile u8 res6[3]; |
| 1012 | volatile u32 ccr; /* PSC + 0x20 */ |
| 1013 | volatile u8 res7[12]; |
| 1014 | volatile u8 ivr; /* PSC + 0x30 */ |
| 1015 | volatile u8 res8[3]; |
| 1016 | volatile u8 ip; /* PSC + 0x34 */ |
| 1017 | volatile u8 res9[3]; |
| 1018 | volatile u8 op1; /* PSC + 0x38 */ |
| 1019 | volatile u8 res10[3]; |
| 1020 | volatile u8 op0; /* PSC + 0x3c */ |
| 1021 | volatile u8 res11[3]; |
| 1022 | volatile u32 sicr; /* PSC + 0x40 */ |
| 1023 | volatile u8 res12[60]; |
| 1024 | volatile u32 tfcmd; /* PSC + 0x80 */ |
| 1025 | volatile u32 tfalarm; /* PSC + 0x84 */ |
| 1026 | volatile u32 tfstat; /* PSC + 0x88 */ |
| 1027 | volatile u32 tfintstat; /* PSC + 0x8C */ |
| 1028 | volatile u32 tfintmask; /* PSC + 0x90 */ |
| 1029 | volatile u32 tfcount; /* PSC + 0x94 */ |
| 1030 | volatile u16 tfwptr; /* PSC + 0x98 */ |
| 1031 | volatile u16 tfrptr; /* PSC + 0x9A */ |
| 1032 | volatile u32 tfsize; /* PSC + 0x9C */ |
| 1033 | volatile u8 res13[28]; |
| 1034 | union { /* PSC + 0xBC */ |
| 1035 | volatile u8 buffer_8; |
| 1036 | volatile u16 buffer_16; |
| 1037 | volatile u32 buffer_32; |
| 1038 | } tfdata_buffer; |
| 1039 | #define tfdata_8 tfdata_buffer.buffer_8 |
| 1040 | #define tfdata_16 tfdata_buffer.buffer_16 |
| 1041 | #define tfdata_32 tfdata_buffer.buffer_32 |
| 1042 | |
| 1043 | volatile u32 rfcmd; /* PSC + 0xC0 */ |
| 1044 | volatile u32 rfalarm; /* PSC + 0xC4 */ |
| 1045 | volatile u32 rfstat; /* PSC + 0xC8 */ |
| 1046 | volatile u32 rfintstat; /* PSC + 0xCC */ |
| 1047 | volatile u32 rfintmask; /* PSC + 0xD0 */ |
| 1048 | volatile u32 rfcount; /* PSC + 0xD4 */ |
| 1049 | volatile u16 rfwptr; /* PSC + 0xD8 */ |
| 1050 | volatile u16 rfrptr; /* PSC + 0xDA */ |
| 1051 | volatile u32 rfsize; /* PSC + 0xDC */ |
| 1052 | volatile u8 res18[28]; |
| 1053 | union { /* PSC + 0xFC */ |
| 1054 | volatile u8 buffer_8; |
| 1055 | volatile u16 buffer_16; |
| 1056 | volatile u32 buffer_32; |
| 1057 | } rfdata_buffer; |
| 1058 | #define rfdata_8 rfdata_buffer.buffer_8 |
| 1059 | #define rfdata_16 rfdata_buffer.buffer_16 |
| 1060 | #define rfdata_32 rfdata_buffer.buffer_32 |
| 1061 | } psc512x_t; |
| 1062 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1063 | /* PSC FIFO Command values */ |
| 1064 | #define PSC_FIFO_RESET_SLICE 0x80 |
| 1065 | #define PSC_FIFO_ENABLE_SLICE 0x01 |
| 1066 | |
| 1067 | /* PSC FIFO Controller Command values */ |
| 1068 | #define FIFOC_ENABLE_CLOCK_GATE 0x01 |
| 1069 | #define FIFOC_DISABLE_CLOCK_GATE 0x00 |
| 1070 | |
| 1071 | /* PSC FIFO status */ |
| 1072 | #define PSC_FIFO_EMPTY 0x01 |
| 1073 | |
| 1074 | /* PSC Command values */ |
| 1075 | #define PSC_RX_ENABLE 0x01 |
| 1076 | #define PSC_RX_DISABLE 0x02 |
| 1077 | #define PSC_TX_ENABLE 0x04 |
| 1078 | #define PSC_TX_DISABLE 0x08 |
| 1079 | #define PSC_SEL_MODE_REG_1 0x10 |
| 1080 | #define PSC_RST_RX 0x20 |
| 1081 | #define PSC_RST_TX 0x30 |
| 1082 | #define PSC_RST_ERR_STAT 0x40 |
| 1083 | #define PSC_RST_BRK_CHG_INT 0x50 |
| 1084 | #define PSC_START_BRK 0x60 |
| 1085 | #define PSC_STOP_BRK 0x70 |
| 1086 | |
| 1087 | /* PSC status register bits */ |
| 1088 | #define PSC_SR_CDE 0x0080 |
| 1089 | #define PSC_SR_TXEMP 0x0800 |
| 1090 | #define PSC_SR_OE 0x1000 |
| 1091 | #define PSC_SR_PE 0x2000 |
| 1092 | #define PSC_SR_FE 0x4000 |
| 1093 | #define PSC_SR_RB 0x8000 |
| 1094 | |
| 1095 | /* PSC mode fields */ |
| 1096 | #define PSC_MODE_5_BITS 0x00 |
| 1097 | #define PSC_MODE_6_BITS 0x01 |
| 1098 | #define PSC_MODE_7_BITS 0x02 |
| 1099 | #define PSC_MODE_8_BITS 0x03 |
| 1100 | #define PSC_MODE_PAREVEN 0x00 |
| 1101 | #define PSC_MODE_PARODD 0x04 |
| 1102 | #define PSC_MODE_PARFORCE 0x08 |
| 1103 | #define PSC_MODE_PARNONE 0x10 |
| 1104 | #define PSC_MODE_ENTIMEOUT 0x20 |
| 1105 | #define PSC_MODE_RXRTS 0x80 |
| 1106 | #define PSC_MODE_1_STOPBIT 0x07 |
| 1107 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 1108 | /* |
| 1109 | * FIFOC |
| 1110 | */ |
| 1111 | typedef struct fifoc512x { |
| 1112 | u32 fifoc_cmd; |
| 1113 | u32 fifoc_int; |
| 1114 | u32 fifoc_dma; |
| 1115 | u32 fifoc_axe; |
| 1116 | u32 fifoc_debug; |
| 1117 | u8 fixme[0xEC]; |
| 1118 | } fifoc512x_t; |
| 1119 | |
| 1120 | /* |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1121 | * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs |
| 1122 | * |
| 1123 | * NOTE: individual PSC units are free to use whatever area (and size) of the |
| 1124 | * FIFOC internal memory, so make sure memory areas for FIFO slices used by |
| 1125 | * different PSCs do not overlap! |
| 1126 | * |
| 1127 | * Overall size of FIFOC memory is not documented in the MPC5121e RM, but |
| 1128 | * tests indicate that it is 1024 words total. |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1129 | * |
| 1130 | * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice. |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1131 | */ |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1132 | #define FIFOC_PSC0_TX_SIZE 0x04 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1133 | #define FIFOC_PSC0_TX_ADDR 0x0 |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1134 | #define FIFOC_PSC0_RX_SIZE 0x04 |
| 1135 | #define FIFOC_PSC0_RX_ADDR 0x10 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1136 | |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1137 | #define FIFOC_PSC1_TX_SIZE 0x04 |
| 1138 | #define FIFOC_PSC1_TX_ADDR 0x20 |
| 1139 | #define FIFOC_PSC1_RX_SIZE 0x04 |
| 1140 | #define FIFOC_PSC1_RX_ADDR 0x30 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1141 | |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1142 | #define FIFOC_PSC2_TX_SIZE 0x04 |
| 1143 | #define FIFOC_PSC2_TX_ADDR 0x40 |
| 1144 | #define FIFOC_PSC2_RX_SIZE 0x04 |
| 1145 | #define FIFOC_PSC2_RX_ADDR 0x50 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1146 | |
| 1147 | #define FIFOC_PSC3_TX_SIZE 0x04 |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1148 | #define FIFOC_PSC3_TX_ADDR 0x60 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1149 | #define FIFOC_PSC3_RX_SIZE 0x04 |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1150 | #define FIFOC_PSC3_RX_ADDR 0x70 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1151 | |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1152 | #define FIFOC_PSC4_TX_SIZE 0x04 |
| 1153 | #define FIFOC_PSC4_TX_ADDR 0x80 |
| 1154 | #define FIFOC_PSC4_RX_SIZE 0x04 |
| 1155 | #define FIFOC_PSC4_RX_ADDR 0x90 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1156 | |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1157 | #define FIFOC_PSC5_TX_SIZE 0x04 |
| 1158 | #define FIFOC_PSC5_TX_ADDR 0xa0 |
| 1159 | #define FIFOC_PSC5_RX_SIZE 0x04 |
| 1160 | #define FIFOC_PSC5_RX_ADDR 0xb0 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1161 | |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1162 | #define FIFOC_PSC6_TX_SIZE 0x04 |
| 1163 | #define FIFOC_PSC6_TX_ADDR 0xc0 |
| 1164 | #define FIFOC_PSC6_RX_SIZE 0x04 |
| 1165 | #define FIFOC_PSC6_RX_ADDR 0xd0 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1166 | |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1167 | #define FIFOC_PSC7_TX_SIZE 0x04 |
| 1168 | #define FIFOC_PSC7_TX_ADDR 0xe0 |
| 1169 | #define FIFOC_PSC7_RX_SIZE 0x04 |
| 1170 | #define FIFOC_PSC7_RX_ADDR 0xf0 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1171 | |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1172 | #define FIFOC_PSC8_TX_SIZE 0x04 |
| 1173 | #define FIFOC_PSC8_TX_ADDR 0x100 |
| 1174 | #define FIFOC_PSC8_RX_SIZE 0x04 |
| 1175 | #define FIFOC_PSC8_RX_ADDR 0x110 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1176 | |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1177 | #define FIFOC_PSC9_TX_SIZE 0x04 |
| 1178 | #define FIFOC_PSC9_TX_ADDR 0x120 |
| 1179 | #define FIFOC_PSC9_RX_SIZE 0x04 |
| 1180 | #define FIFOC_PSC9_RX_ADDR 0x130 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1181 | |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1182 | #define FIFOC_PSC10_TX_SIZE 0x04 |
| 1183 | #define FIFOC_PSC10_TX_ADDR 0x140 |
| 1184 | #define FIFOC_PSC10_RX_SIZE 0x04 |
| 1185 | #define FIFOC_PSC10_RX_ADDR 0x150 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1186 | |
Anatolij Gustschin | ee4aac8 | 2010-04-24 19:27:05 +0200 | [diff] [blame] | 1187 | #define FIFOC_PSC11_TX_SIZE 0x04 |
| 1188 | #define FIFOC_PSC11_TX_ADDR 0x160 |
| 1189 | #define FIFOC_PSC11_RX_SIZE 0x04 |
| 1190 | #define FIFOC_PSC11_RX_ADDR 0x170 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1191 | |
| 1192 | /* |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 1193 | * SATA |
| 1194 | */ |
| 1195 | typedef struct sata512x { |
| 1196 | u8 fixme[0x2000]; |
| 1197 | } sata512x_t; |
| 1198 | |
| 1199 | typedef struct immap { |
| 1200 | sysconf512x_t sysconf; /* System configuration */ |
| 1201 | u8 res0[0x700]; |
| 1202 | wdt512x_t wdt; /* Watch Dog Timer (WDT) */ |
| 1203 | rtclk512x_t rtc; /* Real Time Clock Module */ |
| 1204 | gpt512x_t gpt; /* General Purpose Timer */ |
| 1205 | ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */ |
| 1206 | arbiter512x_t arbiter; /* CSB Arbiter */ |
| 1207 | reset512x_t reset; /* Reset Module */ |
| 1208 | clk512x_t clk; /* Clock Module */ |
| 1209 | pmc512x_t pmc; /* Power Management Control Module */ |
| 1210 | gpio512x_t gpio; /* General purpose I/O module */ |
| 1211 | u8 res1[0x100]; |
| 1212 | mscan512x_t mscan; /* MSCAN */ |
| 1213 | bdlc512x_t bdlc; /* BDLC */ |
| 1214 | sdhc512x_t sdhc; /* SDHC */ |
| 1215 | spdif512x_t spdif; /* SPDIF */ |
| 1216 | i2c512x_t i2c; /* I2C Controllers */ |
| 1217 | u8 res2[0x800]; |
| 1218 | axe512x_t axe; /* AXE */ |
| 1219 | diu512x_t diu; /* Display Interface Unit */ |
| 1220 | cfm512x_t cfm; /* Clock Frequency Measurement */ |
| 1221 | u8 res3[0x500]; |
| 1222 | fec512x_t fec; /* Fast Ethernet Controller */ |
| 1223 | ulpi512x_t ulpi; /* USB ULPI */ |
| 1224 | u8 res4[0xa00]; |
| 1225 | utmi512x_t utmi; /* USB UTMI */ |
| 1226 | u8 res5[0x1000]; |
| 1227 | pcidma512x_t pci_dma; /* PCI DMA */ |
| 1228 | pciconf512x_t pci_conf; /* PCI Configuration */ |
| 1229 | u8 res6[0x80]; |
| 1230 | ios512x_t ios; /* PCI Sequencer */ |
| 1231 | pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ |
| 1232 | u8 res7[0xa00]; |
| 1233 | ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ |
| 1234 | ioctrl512x_t io_ctrl; /* IO Control */ |
| 1235 | iim512x_t iim; /* IC Identification module */ |
| 1236 | u8 res8[0x4000]; |
| 1237 | lpc512x_t lpc; /* LocalPlus Controller */ |
| 1238 | pata512x_t pata; /* Parallel ATA */ |
| 1239 | u8 res9[0xd00]; |
| 1240 | psc512x_t psc[12]; /* PSCs */ |
| 1241 | u8 res10[0x300]; |
| 1242 | fifoc512x_t fifoc; /* FIFO Controller */ |
| 1243 | u8 res11[0x2000]; |
| 1244 | dma512x_t dma; /* DMA */ |
| 1245 | u8 res12[0xa800]; |
| 1246 | sata512x_t sata; /* Serial ATA */ |
| 1247 | u8 res13[0xde000]; |
| 1248 | } immap_t; |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 1249 | |
| 1250 | /* provide interface to get PATA base address */ |
| 1251 | static inline u32 get_pata_base (void) |
| 1252 | { |
| 1253 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
| 1254 | return (u32)(&im->pata); |
| 1255 | } |
| 1256 | #endif /* __ASSEMBLY__ */ |
| 1257 | |
Damien Dusha | 7c3be66 | 2010-10-14 15:27:06 +0200 | [diff] [blame] | 1258 | #define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000 |
| 1259 | #define CONFIG_SYS_MPC512x_USB_ADDR \ |
| 1260 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET) |
| 1261 | |
Benoît Thébaudeau | 7ee151d | 2013-04-23 10:17:41 +0000 | [diff] [blame] | 1262 | #define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim)) |
| 1263 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 1264 | #endif /* __IMMAP_512x__ */ |