blob: 2e155ed9ec4906cfa72d869176c7511c04d51e16 [file] [log] [blame]
David Huang61098202022-01-25 20:56:31 +05301/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * K3: J721S2 SoC definitions, structures etc.
4 *
5 * (C) Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
6 */
7#ifndef __ASM_ARCH_J721S2_HARDWARE_H
8#define __ASM_ARCH_J721S2_HARDWARE_H
9
10#include <config.h>
11#ifndef __ASSEMBLY__
12#include <linux/bitops.h>
13#endif
14
Andrew Davis990ec702022-10-07 14:22:05 -050015#define WKUP_CTRL_MMR0_BASE 0x43000000
16#define MCU_CTRL_MMR0_BASE 0x40f00000
David Huang61098202022-01-25 20:56:31 +053017#define CTRL_MMR0_BASE 0x00100000
David Huang61098202022-01-25 20:56:31 +053018
Andrew Davis990ec702022-10-07 14:22:05 -050019#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
David Huang61098202022-01-25 20:56:31 +053020#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
21#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
22#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
23#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
24#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
25#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
26#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7)
27#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
28
David Huang61098202022-01-25 20:56:31 +053029#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
30#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
31#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
32#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
33#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
34
David Huang61098202022-01-25 20:56:31 +053035/* ROM HANDOFF Structure location */
Bryan Brattlof270537c2022-11-22 13:28:11 -060036#define ROM_EXTENDED_BOOT_DATA_INFO 0x41cfdb00
David Huang61098202022-01-25 20:56:31 +053037
38/* MCU SCRATCHPAD usage */
39#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
40
41#endif /* __ASM_ARCH_J721S2_HARDWARE_H */