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git01.mediatek.com / filogic / uboot / 4a4ebe308448b62123703d49355feffe3f9b1590 / . / arch / arm / dts / omap5-u-boot.dtsi
blob: 720e79b3a55805d3849cbd19be22553e5bd878d7 [file] [log] [blame]
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "dra7.dtsi"
8 */
9
Tero Kristof6c7fda2020-06-16 11:03:10 +0300[diff] [blame]10#ifdef CONFIG_DRA7XX
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]11/{
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]12 chosen {
13 tick-timer = &timer2;
14 };
15
Jean-Jacques Hiblot195df5f2018-12-15 17:43:28 +0100[diff] [blame]16 aliases {
17 usb0 = &usb1;
18 usb1 = &usb2;
19 };
20
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]21 ocp {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
Jean-Jacques Hiblot97f038d2017-04-24 11:51:30 +0200[diff] [blame]23
Jean-Jacques Hiblot0faa1f12018-11-29 10:57:43 +0100[diff] [blame]24 ocp2scp@4a080000 {
25 compatible = "ti,omap-ocp2scp", "simple-bus";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Jean-Jacques Hiblot0faa1f12018-11-29 10:57:43 +0100[diff] [blame]27 };
28
Jean-Jacques Hiblot97f038d2017-04-24 11:51:30 +0200[diff] [blame]29 ocp2scp@4a090000 {
30 compatible = "ti,omap-ocp2scp", "simple-bus";
31 };
Faiz Abbasddbda7a2017-11-14 16:12:32 +0530[diff] [blame]32
33 bandgap@4a0021e0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Faiz Abbasddbda7a2017-11-14 16:12:32 +0530[diff] [blame]35 };
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]36 };
37};
38
39&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]41 reg-shift = <2>;
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]42};
43
44&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]46 reg-shift = <2>;
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]47};
48
49&mmc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]51};
52
53&mmc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]55};
56
57&l4_cfg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]59};
60
61&scm {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]63};
64
65&scm_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]67};
68
69&qspi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]71
72 m25p80@0 {
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]73 compatible = "jedec,spi-nor";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Lokesh Vutla3f332182017-02-10 20:37:18 +0530[diff] [blame]75 };
76};
Lokesh Vutlae6731892017-06-27 13:50:58 +0530[diff] [blame]77
Lokesh Vutla7707fa02017-09-21 08:22:35 +0530[diff] [blame]78&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Lokesh Vutla7707fa02017-09-21 08:22:35 +0530[diff] [blame]80};
81
Lokesh Vutlae6731892017-06-27 13:50:58 +0530[diff] [blame]82&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Lokesh Vutlae6731892017-06-27 13:50:58 +0530[diff] [blame]84};
85
Lokesh Vutla7707fa02017-09-21 08:22:35 +0530[diff] [blame]86&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-pre-ram;
Lokesh Vutla7707fa02017-09-21 08:22:35 +0530[diff] [blame]88};
89
90&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Lokesh Vutla7707fa02017-09-21 08:22:35 +0530[diff] [blame]92};
93
94&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Lokesh Vutla7707fa02017-09-21 08:22:35 +0530[diff] [blame]96};
97
98&gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Lokesh Vutla7707fa02017-09-21 08:22:35 +0530[diff] [blame]100};
101
Lokesh Vutlae6731892017-06-27 13:50:58 +0530[diff] [blame]102&gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Lokesh Vutlae6731892017-06-27 13:50:58 +0530[diff] [blame]104};
Jean-Jacques Hiblot424d6aa2018-12-07 14:50:44 +0100[diff] [blame]105
106&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-pre-ram;
Jean-Jacques Hiblot424d6aa2018-12-07 14:50:44 +0100[diff] [blame]108};
Tero Kristof6c7fda2020-06-16 11:03:10 +0300[diff] [blame]109
110#else /* OMAP54XX */
111&l4_cfg {
112 segment@0 {
113 /* SCM Core */
114 target-module@2000 {
115 compatible = "simple-bus";
116 };
117
118 /* USB HS */
119 target-module@64000 {
120 compatible = "simple-bus";
121 };
122 };
123};
124
125&l4_per {
126 segment@0 {
127 /* UART3 */
128 target-module@20000 {
129 compatible = "simple-bus";
130 };
131
132 /* I2C1 */
133 target-module@70000 {
134 compatible = "simple-bus";
135 };
136
137 /* MMC1 */
138 target-module@9c000 {
139 compatible = "simple-bus";
140 };
141
142 /* MMC2 */
143 target-module@b4000 {
144 compatible = "simple-bus";
145 };
146 };
147};
148
149#endif