blob: 035282bf0b0029d478db8bf2c6c15d592dc717a9 [file] [log] [blame]
Jagan Teki73d51182021-04-26 18:23:46 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 Jagan Teki <jagan@amarulasolutions.com>
4 */
5
Marcel Ziswilerd56d1172021-10-23 01:15:13 +02006/ {
7 binman: binman {
8 multiple-images;
9 };
10};
11
Marcel Ziswiler6dd051a2022-11-07 22:22:41 +010012&soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -070013 bootph-all;
14 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +053015};
16
17&aips1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070018 bootph-all;
19 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +053020};
21
22&aips2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070023 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +053024};
25
26&aips3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070027 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +053028};
29
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020030&binman {
31 u-boot-spl-ddr {
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +020032 align = <4>;
33 align-size = <4>;
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020034 filename = "u-boot-spl-ddr.bin";
35 pad-byte = <0xff>;
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020036
37 u-boot-spl {
38 align-end = <4>;
Marcel Ziswiler74d5d4f2021-10-23 01:15:15 +020039 filename = "u-boot-spl.bin";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020040 };
41
Peng Fan5db610f42022-07-26 16:41:20 +080042 ddr-1d-imem-fw {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020043 filename = "lpddr4_pmu_train_1d_imem.bin";
Peng Fan68811572022-07-26 16:41:22 +080044 align-end = <4>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +020045 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020046 };
47
Peng Fan5db610f42022-07-26 16:41:20 +080048 ddr-1d-dmem-fw {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020049 filename = "lpddr4_pmu_train_1d_dmem.bin";
Peng Fan68811572022-07-26 16:41:22 +080050 align-end = <4>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +020051 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020052 };
53
Peng Fan5db610f42022-07-26 16:41:20 +080054 ddr-2d-imem-fw {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020055 filename = "lpddr4_pmu_train_2d_imem.bin";
Peng Fan68811572022-07-26 16:41:22 +080056 align-end = <4>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +020057 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020058 };
59
Peng Fan5db610f42022-07-26 16:41:20 +080060 ddr-2d-dmem-fw {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020061 filename = "lpddr4_pmu_train_2d_dmem.bin";
Peng Fan68811572022-07-26 16:41:22 +080062 align-end = <4>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +020063 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020064 };
65 };
66
67 spl {
68 filename = "spl.bin";
69
70 mkimage {
71 args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
72
73 blob {
74 filename = "u-boot-spl-ddr.bin";
75 };
76 };
77 };
78
79 itb {
80 filename = "u-boot.itb";
81
82 fit {
83 description = "Configuration to load ATF before U-Boot";
Marek Vasuta7416eb2023-05-28 23:00:30 +020084#ifndef CONFIG_IMX_HAB
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020085 fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
Marek Vasuta7416eb2023-05-28 23:00:30 +020086#endif
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020087 fit,fdt-list = "of-list";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +020088 #address-cells = <1>;
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020089
90 images {
91 uboot {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020092 arch = "arm64";
93 compression = "none";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +020094 description = "U-Boot (64-bit)";
Simon Glass72cc5382022-10-20 18:22:39 -060095 load = <CONFIG_TEXT_BASE>;
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +020096 type = "standalone";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020097
Patrick Wildta6ca6912022-01-13 15:22:17 +010098 uboot-blob {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +020099 filename = "u-boot-nodtb.bin";
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200100 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200101 };
102 };
103
Marek Vasut1de0eb12022-12-22 01:46:37 +0100104#ifndef CONFIG_ARMV8_PSCI
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200105 atf {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200106 arch = "arm64";
107 compression = "none";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200108 description = "ARM Trusted Firmware";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200109 entry = <0x920000>;
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200110 load = <0x920000>;
111 type = "firmware";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200112
Patrick Wildta6ca6912022-01-13 15:22:17 +0100113 atf-blob {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200114 filename = "bl31.bin";
Marcel Ziswilerd87d2f12022-04-08 10:06:56 +0200115 type = "atf-bl31";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200116 };
117 };
Marek Vasut1de0eb12022-12-22 01:46:37 +0100118#endif
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200119
120 binman_fip: fip {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200121 arch = "arm64";
122 compression = "none";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200123 description = "Trusted Firmware FIP";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200124 load = <0x40310000>;
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200125 type = "firmware";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200126 };
127
128 @fdt-SEQ {
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200129 compression = "none";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200130 description = "NAME";
131 type = "flat_dt";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200132
Patrick Wildta6ca6912022-01-13 15:22:17 +0100133 uboot-fdt-blob {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200134 filename = "u-boot.dtb";
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200135 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200136 };
137 };
138 };
139
140 configurations {
141 default = "@config-DEFAULT-SEQ";
142
143 binman_configuration: @config-SEQ {
144 description = "NAME";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200145 fdt = "fdt-SEQ";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200146 firmware = "uboot";
Marek Vasut1de0eb12022-12-22 01:46:37 +0100147#ifndef CONFIG_ARMV8_PSCI
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200148 loadables = "atf";
Marek Vasut1de0eb12022-12-22 01:46:37 +0100149#endif
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200150 };
151 };
152 };
153 };
154
155 imx-boot {
156 filename = "flash.bin";
157 pad-byte = <0x00>;
158
Mamta Shuklacd76f3a2022-07-12 14:36:18 +0000159#ifdef CONFIG_FSPI_CONF_HEADER
160 fspi_conf_block {
161 filename = CONFIG_FSPI_CONF_FILE;
162 type = "blob-ext";
163 size = <0x1000>;
164 };
165
166 spl {
167 filename = "spl.bin";
168 offset = <0x1000>;
169 type = "blob-ext";
170 };
171
172 binman_uboot: uboot {
173 filename = "u-boot.itb";
174 offset = <0x58C00>;
175 type = "blob-ext";
176 };
177#else
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200178 spl {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200179 filename = "spl.bin";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200180 offset = <0x0>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200181 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200182 };
183
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200184 binman_uboot: uboot {
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200185 filename = "u-boot.itb";
Marcel Ziswiler0e2d37e2021-10-23 01:15:14 +0200186 offset = <0x57c00>;
Marcel Ziswiler3c2534a2021-10-23 01:15:16 +0200187 type = "blob-ext";
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200188 };
Mamta Shuklacd76f3a2022-07-12 14:36:18 +0000189#endif
Marcel Ziswilerd56d1172021-10-23 01:15:13 +0200190 };
191};
192
Jagan Teki73d51182021-04-26 18:23:46 +0530193&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700194 bootph-all;
195 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +0530196 /delete-property/ assigned-clocks;
197 /delete-property/ assigned-clock-parents;
198 /delete-property/ assigned-clock-rates;
199};
200
201&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700202 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +0530203};
204
205&osc_24m {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700206 bootph-all;
207 bootph-pre-ram;
Jagan Teki73d51182021-04-26 18:23:46 +0530208};
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200209
210&spba1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700211 bootph-all;
212 bootph-pre-ram;
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200213};
214
215&spba2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700216 bootph-all;
217 bootph-pre-ram;
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200218};