| Andre Przywara | dd5e8da | 2013-09-19 18:06:41 +0200 | [diff] [blame] | 1 | #ifndef __GIC_V2_H__ |
| 2 | #define __GIC_V2_H__ |
| 3 | |
| 4 | /* register offsets for the ARM generic interrupt controller (GIC) */ |
| 5 | |
| 6 | #define GIC_DIST_OFFSET 0x1000 |
| 7 | #define GICD_CTLR 0x0000 |
| 8 | #define GICD_TYPER 0x0004 |
| 9 | #define GICD_IGROUPRn 0x0080 |
| 10 | #define GICD_SGIR 0x0F00 |
| 11 | |
| 12 | #define GIC_CPU_OFFSET_A9 0x0100 |
| 13 | #define GIC_CPU_OFFSET_A15 0x2000 |
| 14 | #define GICC_CTLR 0x0000 |
| 15 | #define GICC_PMR 0x0004 |
| Andre Przywara | dbbe196 | 2013-09-19 18:06:44 +0200 | [diff] [blame] | 16 | #define GICC_IAR 0x000C |
| 17 | #define GICC_EOIR 0x0010 |
| Andre Przywara | dd5e8da | 2013-09-19 18:06:41 +0200 | [diff] [blame] | 18 | |
| 19 | #endif |