Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) STMicroelectronics 2019 - All Rights Reserved |
| 4 | * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. |
| 5 | */ |
| 6 | |
| 7 | #include "stm32mp153.dtsi" |
| 8 | |
| 9 | / { |
| 10 | soc { |
| 11 | gpu: gpu@59000000 { |
| 12 | compatible = "vivante,gc"; |
| 13 | reg = <0x59000000 0x800>; |
| 14 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| 15 | clocks = <&rcc GPU>, <&rcc GPU_K>; |
| 16 | clock-names = "bus" ,"core"; |
| 17 | resets = <&rcc GPU_R>; |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 18 | }; |
| 19 | |
| 20 | dsi: dsi@5a000000 { |
| 21 | compatible = "st,stm32-dsi"; |
| 22 | reg = <0x5a000000 0x800>; |
| 23 | clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; |
| 24 | clock-names = "pclk", "ref", "px_clk"; |
| 25 | resets = <&rcc DSI_R>; |
| 26 | reset-names = "apb"; |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 27 | #address-cells = <1>; |
| 28 | #size-cells = <0>; |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 29 | status = "disabled"; |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 30 | |
| 31 | ports { |
| 32 | #address-cells = <1>; |
| 33 | #size-cells = <0>; |
| 34 | }; |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 35 | }; |
| 36 | }; |
| 37 | }; |