| developer | 15dd2c8 | 2022-09-09 19:59:16 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2022 MediaTek Inc. |
| 4 | * Author: Sam Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "mt7981.dtsi" |
| 9 | #include <dt-bindings/gpio/gpio.h> |
| 10 | |
| 11 | / { |
| 12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; |
| 14 | model = "mt7981-rfb"; |
| 15 | compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; |
| 16 | chosen { |
| 17 | stdout-path = &uart0; |
| 18 | tick-timer = &timer0; |
| 19 | }; |
| 20 | |
| 21 | reg_3p3v: regulator-3p3v { |
| 22 | compatible = "regulator-fixed"; |
| 23 | regulator-name = "fixed-3.3V"; |
| 24 | regulator-min-microvolt = <3300000>; |
| 25 | regulator-max-microvolt = <3300000>; |
| 26 | regulator-boot-on; |
| 27 | regulator-always-on; |
| 28 | }; |
| 29 | }; |
| 30 | |
| 31 | &uart0 { |
| 32 | status = "okay"; |
| 33 | }; |
| 34 | |
| 35 | &uart1 { |
| 36 | pinctrl-names = "default"; |
| 37 | pinctrl-0 = <&uart1_pins>; |
| 38 | status = "disabled"; |
| 39 | }; |
| 40 | |
| 41 | ð { |
| 42 | status = "okay"; |
| 43 | mediatek,gmac-id = <0>; |
| 44 | phy-mode = "sgmii"; |
| 45 | mediatek,switch = "mt7531"; |
| 46 | reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; |
| 47 | |
| 48 | fixed-link { |
| 49 | speed = <1000>; |
| 50 | full-duplex; |
| 51 | }; |
| 52 | }; |
| 53 | |
| 54 | &pinctrl { |
| 55 | spic_pins: spi1-pins-func-1 { |
| 56 | mux { |
| 57 | function = "spi"; |
| 58 | groups = "spi1_1"; |
| 59 | }; |
| 60 | }; |
| 61 | |
| 62 | uart1_pins: spi1-pins-func-3 { |
| 63 | mux { |
| 64 | function = "uart"; |
| 65 | groups = "uart1_2"; |
| 66 | }; |
| 67 | }; |
| 68 | |
| 69 | /* pin15 as pwm0 */ |
| 70 | one_pwm_pins: one-pwm-pins { |
| 71 | mux { |
| 72 | function = "pwm"; |
| 73 | groups = "pwm0_1"; |
| 74 | }; |
| 75 | }; |
| 76 | |
| 77 | /* pin15 as pwm0 and pin14 as pwm1 */ |
| 78 | two_pwm_pins: two-pwm-pins { |
| 79 | mux { |
| 80 | function = "pwm"; |
| 81 | groups = "pwm0_1", "pwm1_0"; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */ |
| 86 | three_pwm_pins: three-pwm-pins { |
| 87 | mux { |
| 88 | function = "pwm"; |
| 89 | groups = "pwm0_1", "pwm1_0", "pwm2"; |
| 90 | }; |
| 91 | }; |
| 92 | |
| 93 | mmc0_pins_default: mmc0default { |
| 94 | mux { |
| 95 | function = "flash"; |
| 96 | groups = "emmc_45"; |
| 97 | }; |
| 98 | conf-cmd-dat { |
| 99 | pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", |
| 100 | "SPI0_CS", "SPI0_HOLD", "SPI0_WP", |
| 101 | "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; |
| 102 | input-enable; |
| 103 | drive-strength = <MTK_DRIVE_4mA>; |
| 104 | bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
| 105 | }; |
| 106 | conf-clk { |
| 107 | pins = "SPI1_CS"; |
| 108 | drive-strength = <MTK_DRIVE_6mA>; |
| 109 | bias-pull-down = <MTK_PUPD_SET_R1R0_10>; |
| 110 | }; |
| 111 | conf-rst { |
| 112 | pins = "PWM0"; |
| 113 | drive-strength = <MTK_DRIVE_4mA>; |
| 114 | bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
| 115 | }; |
| 116 | }; |
| 117 | }; |
| 118 | |
| 119 | &pwm { |
| 120 | pinctrl-names = "default"; |
| 121 | pinctrl-0 = <&two_pwm_pins>; |
| 122 | status = "okay"; |
| 123 | }; |
| 124 | |
| 125 | &watchdog { |
| 126 | status = "disabled"; |
| 127 | }; |
| 128 | |
| 129 | &mmc0 { |
| 130 | pinctrl-names = "default"; |
| 131 | pinctrl-0 = <&mmc0_pins_default>; |
| 132 | bus-width = <8>; |
| 133 | max-frequency = <52000000>; |
| 134 | cap-mmc-highspeed; |
| 135 | cap-mmc-hw-reset; |
| 136 | vmmc-supply = <®_3p3v>; |
| 137 | non-removable; |
| 138 | status = "okay"; |
| 139 | }; |