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git01.mediatek.com / filogic / uboot / 4a33795f89bfe869558345caa0cc43d52027e2a1 / . / arch / arm / dts / imx8mp-evk-u-boot.dtsi
blob: 6784ed2e7c92a4b7e73133637e2a061f5b70c217 [file] [log] [blame]
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]3 * Copyright 2019, 2021 NXP
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]4 */
5
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]6#include "imx8mp-u-boot.dtsi"
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]7
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]8/ {
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]13 };
Clement Faurea93b0d92021-03-25 17:30:33 +0800[diff] [blame]14 firmware {
15 optee {
16 compatible = "linaro,optee-tz";
17 method = "smc";
18 };
19 };
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]20};
21
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]22&reg_usdhc2_vmmc {
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]23 u-boot,off-on-delay-us = <20000>;
24};
25
26&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]28};
29
30&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]32};
33
34&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]36};
37
38&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]40};
41
42&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]44};
45
Peng Fane22df442022-05-05 19:05:59 +0800[diff] [blame]46&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Peng Fane22df442022-05-05 19:05:59 +0800[diff] [blame]48};
49
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]50&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]52};
53
54&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]56};
57
58&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]60};
61
62&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]64};
65
66&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]68};
69
70&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]72};
73
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]74&crypto {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]76};
77
78&sec_jr0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]80};
81
82&sec_jr1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]84};
85
86&sec_jr2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-pre-ram;
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]88};
89
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]90&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]92};
93
94&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]96};
97
98&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]100};
101
102&i2c4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]104};
105
106&i2c5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]108};
109
110&i2c6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]112};
113
114&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]116};
117
118&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]119 bootph-pre-ram;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]120 sd-uhs-sdr104;
121 sd-uhs-ddr50;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]122};
123
124&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]126 mmc-hs400-1_8v;
127 mmc-hs400-enhanced-strobe;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]128};
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]129
130&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]131 bootph-pre-ram;
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]132};
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]133
Ye Li25804942021-08-16 18:44:28 +0800[diff] [blame]134&ethphy0 {
135 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
136 reset-delay-us = <15000>;
137 reset-post-delay-us = <100000>;
138};
139
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]140&fec {
141 phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
Ye Lid1b82062021-02-18 22:33:48 -0800[diff] [blame]142 phy-reset-duration = <15>;
143 phy-reset-post-delay = <100>;
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]144};
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]145
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]146